公开(公告)号：US10579470B1

公开(公告)日：2020-03-03

申请号：US16046927

申请日：2018-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： John M. MacLaren ,  Carl Nels Olson

IPC: G06F11/10 ,  G06F3/06

Abstract: Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.

公开(公告)号：US10769013B1

公开(公告)日：2020-09-08

申请号：US16005427

申请日：2018-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： John M. MacLaren ,  Landon Laws ,  Carl Nels Olson ,  Thomas J. Shepherd

IPC: G06F11/10 ,  G06F12/0802 ,  G06F3/06 ,  G06F11/22

Abstract: Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.