公开(公告)号：US10303543B1

公开(公告)日：2019-05-28

申请号：US15609539

申请日：2017-05-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： John M. MacLaren

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/09 ,  G06F11/30 ,  G06F11/34

Abstract: A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.

公开(公告)号：US10579470B1

公开(公告)日：2020-03-03

申请号：US16046927

申请日：2018-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： John M. MacLaren ,  Carl Nels Olson

IPC: G06F11/10 ,  G06F3/06

Abstract: Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.

公开(公告)号：US10769013B1

公开(公告)日：2020-09-08

申请号：US16005427

申请日：2018-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： John M. MacLaren ,  Landon Laws ,  Carl Nels Olson ,  Thomas J. Shepherd

IPC: G06F11/10 ,  G06F12/0802 ,  G06F3/06 ,  G06F11/22

Abstract: Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.

公开(公告)号：US10534565B1

公开(公告)日：2020-01-14

申请号：US15951107

申请日：2018-04-11

Applicant: Cadence Design Systems, Inc.

Inventor： Bikram Banerjee ,  Anne Hughes ,  John M. MacLaren

IPC: G06F3/06 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4076

Abstract: A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.