公开(公告)号：US10528689B1

公开(公告)日：2020-01-07

申请号：US15364049

申请日：2016-11-29

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Vivek Chickermane ,  Dhruv Dua ,  Krishna Vijaya Chakravadhanula

IPC: G06F17/50

Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.