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    Method for dividing testable logic into a two-dimensional grid for physically efficient scan
    3.
    发明授权
    Method for dividing testable logic into a two-dimensional grid for physically efficient scan 有权
    将可测试逻辑分为二维网格以进行物理高效扫描的方法

    公开(公告)号：US09470755B1

    公开(公告)日：2016-10-18

    申请号：US14738746

    申请日：2015-06-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Brian Edward Foutz ,  Steev Wilcox ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula ,  Paul Alexander Cunningham

    IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

    CPC classification number: G06F17/5077 ,  G01R31/318335 ,  G01R31/318558 ,  G01R31/318583

    Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

    Abstract translation: 用于实现集成电路设计的物理高效扫描的方法和计算机可读介质可以包括选择二维网格尺寸以暴露于该方法，二维网格具有包括第一侧长度，第二边长度， 和一些翻牌。 执行该方法以选择使压缩效率最大化并限制IC上的布线拥塞的二维网格尺寸。 一方面，可以在网格的每个区域上执行该方法，该区域维持相应的第一边长和相应的第二边长大于1的区域，包括选择较大边，确定较大边是奇数还是偶数， 并且将较大侧的网格划分成每个具有翻牌比例的两个区域。 所得区域的扫描是有效的，因此有助于集成电路设计和随后的制造。

    Method for using sequential decompression logic for VLSI test in a physically efficient construction
    5.
    发明授权
    Method for using sequential decompression logic for VLSI test in a physically efficient construction 有权
    在物理有效的结构中使用顺序解压缩逻辑进行VLSI测试的方法

    公开(公告)号：US09470756B1

    公开(公告)日：2016-10-18

    申请号：US14738765

    申请日：2015-06-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Steev Wilcox ,  Brian Edward Foutz ,  Krishna Vijaya Chakravadhanula ,  Vivek Chickermane ,  Paul Alexander Cunningham

    IPC: G01R31/28 ,  G01R31/3177

    CPC classification number: G01R31/318563 ,  G01R31/318547 ,  G01R31/318583

    Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

    Abstract translation: 用于在“测试设计”（DFT）应用中解压缩一组扫描输入数据的方法，系统和集成电路，其中实现可以包括从自动测试设备（ATE）确定应用电路的扫描输入的数量。 基于扫描输入的数量，实现的另一方面可以涉及在集成电路（IC）上生成二维网格。 另一个实现方面可以包括根据依次分布的解压缩逻辑从ATE解压缩扫描输入，使得网格可以在本地应用解压缩逻辑的最后阶段。 根据该方法的方面，IC解压缩逻辑的物理结构对于各个扫描链更易于访问，并减少IC上的拥塞。

    Method to improve testability using 2-dimensional exclusive or (XOR) grids
    6.
    发明授权
    Method to improve testability using 2-dimensional exclusive or (XOR) grids 有权

    公开(公告)号：US10955470B1

    公开(公告)日：2021-03-23

    申请号：US16218954

    申请日：2018-12-13

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Brian Edward Foutz ,  Christos Papameletis ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

    IPC: G01R31/3177 ,  G01R31/317 ,  G06F30/33 ,  G06F30/392 ,  G06F30/398

    Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

    Method for optimally connecting scan segments in two-dimensional compression chains
    7.
    发明授权
    Method for optimally connecting scan segments in two-dimensional compression chains 有权

    公开(公告)号：US10761131B1

    公开(公告)日：2020-09-01

    申请号：US16140701

    申请日：2018-09-25

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Christos Papameletis ,  Brian Edward Foutz ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

    IPC: G01R31/28 ,  G01R31/3177 ,  G06F30/398

    Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

    Method for using XOR trees for physically efficient scan compression and decompression logic
    8.
    发明授权
    Method for using XOR trees for physically efficient scan compression and decompression logic 有权
    使用XOR树进行物理高效的扫描压缩和解压缩逻辑的方法

    公开(公告)号：US09513335B1

    公开(公告)日：2016-12-06

    申请号：US14738763

    申请日：2015-06-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Steev Wilcox ,  Brian Edward Foutz ,  Paul Alexander Cunningham ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

    IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

    CPC classification number: G01R31/318547

    Abstract: Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

    Abstract translation: 公开了使用XOR树解压缩测试数据的方法和装置，用于在物理上有效的结构中应用于测试（DFT）集成电路设计的扫描链。 此外，公开了用于在物理上有效的结构中的DFT集成电路中的来自扫描链的测试响应数据的压缩方法和装置。 XOR树解压缩方法可以包括根据由一组异或门实现的分布逻辑在XOR树的每个节点处分离信号。 XOR树压缩方法可以包括根据由一组异或门实现的组合逻辑在XOR树的每个节点处组合信号。

    Low-power shift with clock staggering
    10.
    发明授权
    Low-power shift with clock staggering 有权

    公开(公告)号：US10775435B1

    公开(公告)日：2020-09-15

    申请号：US16177621

    申请日：2018-11-01

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Christos Papameletis ,  Brian Edward Foutz ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

    IPC: G01R31/3185

    Abstract: Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).

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