公开(公告)号：US11520964B1

公开(公告)日：2022-12-06

申请号：US17336315

申请日：2021-06-02

Applicant: Cadence Design Systems, Inc.

Inventor： Ahmad S. Abo Foul ,  Lars Lundgren ,  Björn Håkan Hjort ,  Habeeb Farah ,  Eran Talmor ,  Paula S. Mathias

IPC: G06F30/3323 ,  H04L9/06

Abstract: A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version of the model of the electronic device and presenting as a status result for each the instantiations of a plurality of the properties of the current version of the model of the electronic design the preferred status result obtained for that instantiation of the property per the same unique signature value that was calculated for that instantiation of the property in previous runs of the plurality of formal verification regression runs.