公开(公告)号：US11520964B1

公开(公告)日：2022-12-06

申请号：US17336315

申请日：2021-06-02

Applicant: Cadence Design Systems, Inc.

Inventor： Ahmad S. Abo Foul ,  Lars Lundgren ,  Björn Håkan Hjort ,  Habeeb Farah ,  Eran Talmor ,  Paula S. Mathias

IPC: G06F30/3323 ,  H04L9/06

Abstract: A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version of the model of the electronic device and presenting as a status result for each the instantiations of a plurality of the properties of the current version of the model of the electronic design the preferred status result obtained for that instantiation of the property per the same unique signature value that was calculated for that instantiation of the property in previous runs of the plurality of formal verification regression runs.

公开(公告)号：US11023357B1

公开(公告)日：2021-06-01

申请号：US16583853

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Ayman Hanna ,  Karam Abdelkader ,  Doron Bustan ,  Habeeb Farah ,  Thiago Radicchi Roque ,  Felipe Althoff

IPC: G06F11/36 ,  G06N20/00 ,  G06F30/30 ,  G06F30/33 ,  G06F30/333

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

公开(公告)号：US10983758B1

公开(公告)日：2021-04-20

申请号：US16538900

申请日：2019-08-13

Applicant: Cadence Design Systems, Inc.

Inventor： Rajdeep Mukherjee ,  Benjamin Meng-Ching Chen ,  Habeeb Farah ,  Ziyad Hanna

IPC: G06F8/20 ,  G06F8/10

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a reference model including a software specification and an implementation model at a register transfer level. Embodiments may also include generating one or more invariants based upon, at least in part, the reference model, wherein generating one or more invariants includes applying a semantic analysis. Embodiments may further include automatically generating at least one case splitting candidate based upon, at least in part, the one or more generated invariants.

公开(公告)号：US10782767B1

公开(公告)日：2020-09-22

申请号：US16176645

申请日：2018-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Karam Abd Elkader ,  Doron Bustan ,  Habeeb Farah ,  Yaron Schiller

IPC: G06F1/00 ,  G06F1/3237

Abstract: The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of flip-flops from the plurality of flip-flops and disabling a second clock associated with the second set of flip-flops without changing a value of the second set of flip-flops. Embodiments may further include determining whether a first output from the first set of flip-flops and a second output from the second set of flip-flops have converged.

公开(公告)号：US11514219B1

公开(公告)日：2022-11-29

申请号：US17212150

申请日：2021-03-25

Applicant: Cadence Design Systems, Inc.

Inventor： Ahmad S. Abo Foul ,  Lars Lundgren ,  Björn Håkan Hjort ,  Habeeb Farah

IPC: G06F30/3323

Abstract: The present disclosure relates to a system and method for assertion-based formal verification in an electronic design environment. Embodiments may include executing, using a processor, an assertion-based formal verification proof process on a model of an electronic design and analyzing a first property associated with the model. Embodiments may further include generating at least one trace of the first property and determining a mapping function associated with the first property. Embodiments may also include storing the at least one trace and the mapping function. Embodiments may further include determining that a second property associated with the model shares a cone of influence with the first property and generating a new trace based upon, at least in part, the mapping function.

公开(公告)号：US11080448B1

公开(公告)日：2021-08-03

申请号：US16910815

申请日：2020-06-24

Applicant: Cadence Design Systems, Inc.

Inventor： Yaron Schiller ,  Guy Wolfovitz ,  Habeeb Farah

IPC: G06F30/30 ,  G06F30/3323 ,  G06F111/08 ,  G06F7/58

Abstract: A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.

公开(公告)号：US10853546B1

公开(公告)日：2020-12-01

申请号：US16583937

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Yaron Schiller ,  Almothana Sirhan ,  Karam Abdelkader ,  Habeeb Farah ,  Thiago Radicchi Roque

IPC: G06F30/3323 ,  G06F30/33

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.

公开(公告)号：US10984161B1

公开(公告)日：2021-04-20

申请号：US16689410

申请日：2019-11-20

Applicant: Cadence Design Systems, Inc.

Inventor： Rajdeep Mukherjee ,  Ravi Prakash ,  Benjamin Meng-Ching Chen ,  Habeeb Farah ,  Ziyad Hanna

IPC: G06F30/3323 ,  G06F111/02 ,  G06F119/16

Abstract: The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.

公开(公告)号：US10789404B1

公开(公告)日：2020-09-29

申请号：US16434129

申请日：2019-06-06

Applicant: Cadence Design Systems, Inc.

Inventor： Rajdeep Mukherjee ,  Benjamin Meng-Ching Chen ,  Habeeb Farah ,  Ziyad Hanna

IPC: G06F17/50 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/327 ,  G06F30/31 ,  G06F30/323 ,  G06F30/30 ,  G06F111/02 ,  G06F119/16

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.

公开(公告)号：US10546083B1

公开(公告)日：2020-01-28

申请号：US15591293

申请日：2017-05-10

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Verma ,  Suyash Kumar ,  Habeeb Farah

IPC: G06F17/50 ,  H01L27/02

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.