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公开(公告)号：US11436402B1
公开(公告)日：2022-09-06
申请号：US17219695
申请日：2021-03-31
Applicant: Cadence Design Systems, Inc.
Inventor： Miao Liu , Liqun Deng , Guozhi Xu
IPC: G06F30/392 , G06F30/31 , G06F119/12
Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.
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