公开(公告)号：US11436402B1

公开(公告)日：2022-09-06

申请号：US17219695

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Miao Liu ,  Liqun Deng ,  Guozhi Xu

IPC: G06F30/392 ,  G06F30/31 ,  G06F119/12

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

公开(公告)号：US11276677B1

公开(公告)日：2022-03-15

申请号：US16789296

申请日：2020-02-12

Applicant: Cadence Design Systems, Inc.

Inventor： Liqun Deng ,  Pinhong Chen ,  Richard M. Chou ,  Chin-Chih Chang ,  Miao Liu ,  Yufeng Luo

IPC: G06F30/394 ,  G06F30/398 ,  H01L27/02 ,  H01L25/065 ,  G06F111/04 ,  G06F111/00 ,  G06F30/39

Abstract: Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.