公开(公告)号：US12216977B1

公开(公告)日：2025-02-04

申请号：US17831287

申请日：2022-06-02

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Hongxin Kong ,  Mehmet Can Yildiz

IPC: G06F30/392 ,  G06F30/3947 ,  G06F111/04

Abstract: Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed based on the maximum turn constraint. The routing of the net results in a routed net comprising a connection path between the first pin and the second pin that includes a number of turns that satisfy the maximum turn constraint. A layout instance for the integrated circuit design is generated based in part on the routed net.