公开(公告)号：US11132489B1

公开(公告)日：2021-09-28

申请号：US16805155

申请日：2020-02-28

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Yi-Xiao Ding ,  Zhuo Li ,  Mehmet Can Yildiz

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/392

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

公开(公告)号：US10460065B1

公开(公告)日：2019-10-29

申请号：US15649426

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

公开(公告)号：US10289795B1

公开(公告)日：2019-05-14

申请号：US15683659

申请日：2017-08-22

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Thomas Andrew Newton ,  Derong Liu ,  Mehmet Can Yildiz ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.

公开(公告)号：US12216977B1

公开(公告)日：2025-02-04

申请号：US17831287

申请日：2022-06-02

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Hongxin Kong ,  Mehmet Can Yildiz

IPC: G06F30/392 ,  G06F30/3947 ,  G06F111/04

Abstract: Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed based on the maximum turn constraint. The routing of the net results in a routed net comprising a connection path between the first pin and the second pin that includes a number of turns that satisfy the maximum turn constraint. A layout instance for the integrated circuit design is generated based in part on the routed net.

公开(公告)号：US10706201B1

公开(公告)日：2020-07-07

申请号：US16292012

申请日：2019-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Mehmet Can Yildiz

IPC: G06F30/30 ,  G06F30/394

Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.

公开(公告)号：US10685164B1

公开(公告)日：2020-06-16

申请号：US16239310

申请日：2019-01-03

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

公开(公告)号：US10460063B1

公开(公告)日：2019-10-29

申请号：US15649402

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Gracieli Posser ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

公开(公告)号：US11030377B1

公开(公告)日：2021-06-08

申请号：US16895847

申请日：2020-06-08

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Mehmet Can Yildiz

IPC: G06F30/394 ,  G06K9/62

Abstract: Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.

公开(公告)号：US10997352B1

公开(公告)日：2021-05-04

申请号：US16416008

申请日：2019-05-17

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Mehmet Can Yildiz ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Zhuo Li ,  Derong Liu

IPC: G06F30/394 ,  G06F30/18 ,  G06F30/327

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

公开(公告)号：US10460064B1

公开(公告)日：2019-10-29

申请号：US15649415

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.