公开(公告)号：US10255394B1

公开(公告)日：2019-04-09

申请号：US15470732

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Harsh Vardhan ,  Jalal Wehbeh ,  Robert MacDonald

IPC: G06F17/50 ,  G06F9/50

Abstract: A method for simulating an integrated circuit model is provided. The method includes receiving partition netlists of an integrated circuit in a partition scheduler and scheduling, by at least one computer, an execution of a computational thread associated with a first partition netlist. The method also includes preparing input data for a task and storing the input data set in an object storage. Also, the method includes executing, by the computer, the task in the computational thread. The method also includes building dependency trees between multiple tasks for reducing the input/output data overhead, and caching information that may be necessary for each task but may be reusable by the task when such information is unavailable from previously computed tasks.

公开(公告)号：US10769330B1

公开(公告)日：2020-09-08

申请号：US15470639

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jalal Wehbeh ,  Harsh Vardhan ,  Federico Politi ,  Ajish Thomas ,  Aswin Ramakrishnan

IPC: G06F30/33 ,  G06F30/367 ,  G06F30/398 ,  G06F30/39

Abstract: A method for determining signal electromigration in a circuit includes selecting partitions from a netlist of the circuit is provided, each of the partitions including independent signal paths. The method includes determining a size of a partition, applying input vectors to a signal path in a large partition to obtain a signal toggle in an output, determining a current in the signal path, and identifying an electromigration result from the current flow. The method includes generating an output database for the partition, comprising an electromigration result for the first component, and combining the output database for the partition with a second output database from a second partition, the second output database including a second electromigration result for a second component in the second partition to generate an electromigration report for the netlist of the integrated circuit.

公开(公告)号：US10235482B1

公开(公告)日：2019-03-19

申请号：US15470712

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Aswin Ramakrishnan ,  Jalal Wehbeh ,  Robert MacDonald ,  Federico Politi ,  Ajish Thomas

IPC: G06F17/50

Abstract: A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components. When a second input stimulus vector is associated with a second delay arc that is equivalent to the first delay arc in the logic path, the method includes selecting one of the first or second input stimulus vectors for a set of input stimuli vectors. The method further includes determining an electromigration effect on the partition netlist with the input stimuli vectors.

公开(公告)号：US10192012B1

公开(公告)日：2019-01-29

申请号：US15470722

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jalal Wehbeh ,  Aswin Ramakrishnan ,  Igor Keller ,  Federico Politi ,  Ajish Thomas

IPC: G06F17/50

Abstract: A method for determining a signal electromigration effect in a circuit includes obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a complementary netlist that couples a second input with the output is provided. The complementary netlist is logically independent from the reference netlist. The method includes modifying the partition netlist to couple the reference netlist and the complementary netlist in an inverting configuration, and providing an electromagnetic pulse to at least one of the first input or the second input to induce a current through one of the plurality of circuit components. The method also includes determining an electromigration effect from the current on the one of the plurality of circuit components.

公开(公告)号：US10181000B1

公开(公告)日：2019-01-15

申请号：US15470727

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Harsh Vardhan ,  Jalal Wehbeh ,  Ajish Thomas

IPC: G06F17/50

Abstract: A method for determining an electromigration effect in an integrated circuit model with multiple parallel processors is provided. The method includes receiving, in a partition scheduler, a circuit netlist divided into smaller partition netlists in a partition scheduler and scheduling a computational thread including tasks associated with a first partition netlist, and verifying that at least one task in the first computational thread has been executed by at least one computer selected from a network of computers. The method also includes releasing the computer and resetting a status of the computer, converting a result from the at least one task to an input file for another computational thread associated with a second partition netlist, the result including an induced current in the circuit component of the first partition netlist. The method includes determining electromigration effects on the circuit component in the partition netlists based on the induced current.