公开(公告)号：US20140096099A1

公开(公告)日：2014-04-03

申请号：US13632885

申请日：2012-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Joel R. Phillips ,  Qunzeng Liu ,  Igor Keller

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/84

Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

Abstract translation: 提供了一种用于在集成电路设计的静态时序分析期间用于产生等效波形模型的方法，所述方法包括：使用内部组件的模拟模型来模拟内部组件以产生多个模拟仿真输出表征波形作为 用于表征设计单元的多个输入波形的功能; 使用内部组件的模拟模型来模拟内部组件，以产生作为复杂波形的函数的模拟仿真输出波形; 并产生等效波形模型作为多个模拟仿真输出特性波形和模拟仿真输出波形的函数。

公开(公告)号：US11023636B1

公开(公告)日：2021-06-01

申请号：US15931547

申请日：2020-05-13

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Ratnakar Goyal ,  Manuj Verma ,  Harmandeep Singh

IPC: G06F30/3312 ,  G06F119/02

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.

公开(公告)号：US10192012B1

公开(公告)日：2019-01-29

申请号：US15470722

申请日：2017-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jalal Wehbeh ,  Aswin Ramakrishnan ,  Igor Keller ,  Federico Politi ,  Ajish Thomas

IPC: G06F17/50

Abstract: A method for determining a signal electromigration effect in a circuit includes obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a complementary netlist that couples a second input with the output is provided. The complementary netlist is logically independent from the reference netlist. The method includes modifying the partition netlist to couple the reference netlist and the complementary netlist in an inverting configuration, and providing an electromagnetic pulse to at least one of the first input or the second input to induce a current through one of the plurality of circuit components. The method also includes determining an electromigration effect from the current on the one of the plurality of circuit components.

公开(公告)号：US09710593B1

公开(公告)日：2017-07-18

申请号：US14883482

申请日：2015-10-14

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Igor Keller ,  Mikhail Chetin ,  Xiaojun Sun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031

Abstract: Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.

公开(公告)号：US08924905B1

公开(公告)日：2014-12-30

申请号：US13924516

申请日：2013-06-21

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Joel R. Philips ,  Jijun Chen

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F2217/84

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract translation: 在一个实施例中，公开了一种构建用于集成电路设计的静态时序分析的等效波形模型的方法。 该方法包括从定时库中接收来自延迟和转换模型的时间点系数（qk）和已知的时间延迟值; 从定时库确定输入波形的波形值（Ikj）; 响应于定时库的输入波形从定时库中的定时表确定定时值（dj）; 以及通过使延迟方程的残差最小化来确定系数（qk）。

公开(公告)号：US11775719B1

公开(公告)日：2023-10-03

申请号：US17713004

申请日：2022-04-04

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Xiaopeng Dong ,  Sourabh Rajguru

IPC: G06F30/30 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.

公开(公告)号：US10789406B1

公开(公告)日：2020-09-29

申请号：US16193803

申请日：2018-11-16

Applicant: Cadence Design Systems, Inc.

Inventor： Shiva Raja ,  Igor Keller ,  Ling Wang

IPC: G06F30/3323 ,  G06F30/30 ,  G06F30/367 ,  G06F30/3312 ,  G06F111/04 ,  G06F111/10 ,  G06F111/20 ,  G06F119/12

Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.

公开(公告)号：US10430536B1

公开(公告)日：2019-10-01

申请号：US15721148

申请日：2017-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Mikhail Chetin

IPC: G06F17/50

Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

公开(公告)号：US10275554B1

公开(公告)日：2019-04-30

申请号：US15652130

申请日：2017-07-17

Applicant: Cadence Design Systems, Inc.

Inventor： Mikhail Chetin ,  Igor Keller ,  Praveen Ghanta

IPC: G06F17/50 ,  G06F17/15 ,  G06F16/901

Abstract: A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.

公开(公告)号：US09003342B1

公开(公告)日：2015-04-07

申请号：US14230931

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Jijun Chen ,  Dhananjay Griyage

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/84

Abstract: A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.

Abstract translation: 集权侵略者模型用于模拟作用于受害者网络的多个侵略网络。 通过将攻击者网络集中在一个单个输入端口中，可以在静态时序分析期间将单个电压激励施加到输入端口以模拟模型。 然而，维护每个侵略者网络的每个侵略者网络和几个相关属性的记录，使得个体集中攻击者网络仍然可以被建模为对受害者网络的攻击的单独贡献。