公开(公告)号：US11775723B1

公开(公告)日：2023-10-03

申请号：US17364388

申请日：2021-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Pinhong Chen ,  Liqun Deng ,  Ximing Zhou ,  Hanqi Yang ,  Jieqian Yu ,  Fangfang Li

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/396

CPC classification number: G06F30/392 ,  G06F30/31 ,  G06F30/396

Abstract: Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.