公开(公告)号：US08924905B1

公开(公告)日：2014-12-30

申请号：US13924516

申请日：2013-06-21

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Joel R. Philips ,  Jijun Chen

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F2217/84

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract translation: 在一个实施例中，公开了一种构建用于集成电路设计的静态时序分析的等效波形模型的方法。 该方法包括从定时库中接收来自延迟和转换模型的时间点系数（qk）和已知的时间延迟值; 从定时库确定输入波形的波形值（Ikj）; 响应于定时库的输入波形从定时库中的定时表确定定时值（dj）; 以及通过使延迟方程的残差最小化来确定系数（qk）。