公开(公告)号：US11663149B1

公开(公告)日：2023-05-30

申请号：US17526090

申请日：2021-11-15

Applicant: Cadence Design Systems, Inc.

Inventor： John Michael MacLaren ,  Thomas Joseph Shepherd ,  Davika Raghu

IPC: G06F13/16 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/0238 ,  G06F12/0871 ,  G06F12/0882 ,  G06F13/1636

Abstract: Embodiments include herein are directed towards a dynamic random access memory system. Embodiments may include a command queue that is configured to hold all commands that are currently selectable for bank operation and execution. Embodiments may further include bank logic operatively connected with the command queue. The bank logic may include a bank management module and a plurality of bank slices, wherein each of the plurality of bank slices is an independent, re-assignable bank tracking module.

公开(公告)号：US11720287B1

公开(公告)日：2023-08-08

申请号：US17536440

申请日：2021-11-29

Applicant: Cadence Design Systems, Inc.

Inventor： John Michael MacLaren

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/067 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0656

Abstract: Embodiments include herein are directed towards a double data rate (“DDR”) controller system. Embodiments may include a plurality of read data buffers, wherein each of the plurality of read data buffers is configured for read data storage and is of a same size. Embodiments may further include a port read response queue that stores information corresponding to an incoming read and a command queue configured to receive read data buffer state information from the port read response queue. Embodiments may also include a read data buffer allocation tracker configured to track a state of each of the plurality of read data buffers.

公开(公告)号：US10282250B1

公开(公告)日：2019-05-07

申请号：US15808852

申请日：2017-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Bikram Banerjee ,  Anne Rodgers Hughes ,  John Michael MacLaren

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.