公开(公告)号：US08812898B1

公开(公告)日：2014-08-19

申请号：US13628982

申请日：2012-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Manas Lahon ,  Sandeep Brahmadathan

IPC: G06F11/00

CPC classification number: G06F11/1443 ,  G06F11/10 ,  G06F13/28

Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.

Abstract translation: 提供了一种系统和方法，用于通过自动从在整个系统中遍历的数据中检测到的不可纠正的错误并从第一存储器和次要较慢存储器之间的不可靠的中间数据缓冲器中检索来确保可靠的数据传输。 另外，提供了用于补偿使用不可靠或容易出错的组件和互连（例如SRAM存储器作为临时缓冲器）的措施。 此外，提供了检测和纠正错误的措施，无论在整个系统遍历时的任何阶段注入或发生的类型。

公开(公告)号：US10545866B1

公开(公告)日：2020-01-28

申请号：US15639908

申请日：2017-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yoshiharu Kato ,  Manas Lahon ,  Sandeep Brahmadathan

IPC: G06F12/06 ,  G06F1/12

Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.