公开(公告)号：US09811273B1

公开(公告)日：2017-11-07

申请号：US14580833

申请日：2014-12-23

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sandeep Brahmadathan

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1068 ,  G06F2206/1014 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/2254

Abstract: The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.

公开(公告)号：US09471094B1

公开(公告)日：2016-10-18

申请号：US14585548

申请日：2014-12-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sandeep Brahmadathan ,  Jeffrey Scott Earl ,  Todd Barth

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A chip select signal is trained where the chip select signal is delayed to centrally align its pulses with a positive edge of a memory device's clock cycle. Over repeated iterations, the memory device stops its clock for an interval and a delayed pulse of the chip select signal is generated. The pulse delay is incrementally changed with each iteration. When the delay results in the trailing edge of the delayed pulse aligning with the positive edge of the last cycle before the stoppage interval, the memory device captures the contents of a computer bus, thus detecting a trailing edge delay value. When the delay results in the leading edge of the delayed pulse aligning with the positive edge of the last cycle, the device no longer captures the contents, thus detecting a leading edge delay value. A value between these values is then set as the optimal delay.

Abstract translation: 训练芯片选择信号，其中芯片选择信号被延迟以将其脉冲与存储器件的时钟周期的上升沿对齐。 通过重复迭代，存储器件停止其时钟的间隔，并产生片选信号的延迟脉冲。 脉冲延迟随着每次迭代而递增变化。 当延迟导致延迟脉冲的后沿与停止间隔之前的最后一个周期的上升沿对准时，存储器件捕获计算机总线的内容，从而检测后沿延迟值。 当延迟导致延迟脉冲的前沿与最后一个周期的上升沿对齐时，器件不再捕获内容，因此检测前沿延迟值。 然后将这些值之间的值设置为最佳延迟。

公开(公告)号：US09886987B1

公开(公告)日：2018-02-06

申请号：US14585621

申请日：2014-12-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sandeep Brahmadathan ,  Jeffrey Scott Earl

IPC: G11C7/10 ,  G06F1/08

CPC classification number: G11C7/1072 ,  G06F1/08 ,  G11C7/1009 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56012 ,  G11C2207/2254

Abstract: A system and method providing timing alignment of a data mask (DM) signal with respect to a data strobe (DQS) signal for memory devices not designed for adjusting such alignment is provided. Alignment between data signals (DQ) and a DQS signal is first achieved during a first write training procedure where a data delay value is optimized for one of the DQS or DQ signals. Subsequently, using the optimum delay value from the first write training procedure, a second write training procedure is initiated. In the second write training procedure, timing alignment between the DM signal and the DQ signals is achieved by determining an optimal delay value of the DM signal relative to the DQS signal.

公开(公告)号：US08812898B1

公开(公告)日：2014-08-19

申请号：US13628982

申请日：2012-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Manas Lahon ,  Sandeep Brahmadathan

IPC: G06F11/00

CPC classification number: G06F11/1443 ,  G06F11/10 ,  G06F13/28

Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.

Abstract translation: 提供了一种系统和方法，用于通过自动从在整个系统中遍历的数据中检测到的不可纠正的错误并从第一存储器和次要较慢存储器之间的不可靠的中间数据缓冲器中检索来确保可靠的数据传输。 另外，提供了用于补偿使用不可靠或容易出错的组件和互连（例如SRAM存储器作为临时缓冲器）的措施。 此外，提供了检测和纠正错误的措施，无论在整个系统遍历时的任何阶段注入或发生的类型。

公开(公告)号：US10885952B1

公开(公告)日：2021-01-05

申请号：US16727623

申请日：2019-12-26

Applicant: Cadence Design Systems, Inc.

Inventor： Sandeep Brahmadathan ,  Takashi Ueda ,  Jeffrey S. Earl ,  Utpal Mahanta

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.

公开(公告)号：US10545866B1

公开(公告)日：2020-01-28

申请号：US15639908

申请日：2017-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yoshiharu Kato ,  Manas Lahon ,  Sandeep Brahmadathan

IPC: G06F12/06 ,  G06F1/12

Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.

公开(公告)号：US08880980B1

公开(公告)日：2014-11-04

申请号：US13686612

申请日：2012-11-27

Applicant: Cadence Design Systems, Inc.

Inventor： Anish Mathew ,  Sandeep Brahmadathan ,  Raveendra Pai G.

IPC: G11C29/00 ,  H03M13/05 ,  H03M13/15

CPC classification number: H03M13/15 ,  H03M13/13 ,  H03M13/152 ,  H03M13/27

Abstract: A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.

Abstract translation: 提供了一种用于以错误校正的方式从源设备快速传送数据到目的地设备的系统和方法。 该系统和方法在初始化从源设备到目的设备的输入数据传输之前避免了利用中间缓冲器的实质性延迟，确定错误以及修复检测到的错误。 在完成纠错后，只有那些被校正的部分被重新发送到目的地存储器而不是完整的校正输入数据。 提供了一个旁路部分，用于将输入数据复制到目的地存储器，至少具有与通过分离器部分与校正部分耦合的并行缓冲器的输入数据的错误检测的并行度。

公开(公告)号：US09159423B1

公开(公告)日：2015-10-13

申请号：US13631171

申请日：2012-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Sandeep Brahmadathan ,  Srinivas Suresh Revankar

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/04 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to.

Abstract translation: 本发明提供一种减少闪存装置中引入的误差的影响的方法和系统，同时通过使用预定的阈值或阈值装置值对开销的有限影响的优化活动提供改进的系统性能。 在一个实施例中，将设备阈值与具有目标页面的零值的数据位的累积数量进行比较，并且评估目标页面的错误类型以确定目标页面是否可用于被写入。 因此，提供了一种用于确定具有要被识别的块地址和页面地址的页面的可用性的高效方法，在一个实例中，作为可被写入的擦除页面。