公开(公告)号：US09721048B1

公开(公告)日：2017-08-01

申请号：US14864249

申请日：2015-09-24

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell Grant Poplack ,  Yuhei Hayashi ,  Mark Alton Sherred

IPC: G06F17/50 ,  G06F12/0877 ,  G06F15/80

CPC classification number: G06F17/5045 ,  G06F12/0877 ,  G06F15/8007 ,  G06F15/8053 ,  G06F17/5027 ,  G06F2212/1016 ,  G06F2217/86

Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a sequence of commands and/or data blocks to the channel buffers, the associated processors can execute programs of varying complexity that may have been written or modified in real time or preconfigured.