公开(公告)号：US11740973B2

公开(公告)日：2023-08-29

申请号：US17173093

申请日：2021-02-10

Applicant: Cadence Design Systems, Inc.

Inventor： Matthew B. Smittle ,  Jama Ismail Barreh ,  Robert T. Golla

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/38 ,  G06F11/07

CPC classification number: G06F11/1405 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/0766 ,  G06F11/0751

Abstract: An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

公开(公告)号：US20230350605A1

公开(公告)日：2023-11-02

申请号：US17661402

申请日：2022-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Matthew B. Smittle

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.

公开(公告)号：US20230342296A1

公开(公告)日：2023-10-26

申请号：US17660775

申请日：2022-04-26

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Matthew B. Smittle

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

公开(公告)号：US12141474B2

公开(公告)日：2024-11-12

申请号：US17661402

申请日：2022-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Matthew B. Smittle

IPC: G06F3/06

Abstract: A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.

公开(公告)号：US11960400B2

公开(公告)日：2024-04-16

申请号：US17660775

申请日：2022-04-26

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Matthew B. Smittle

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

公开(公告)号：US11537505B2

公开(公告)日：2022-12-27

申请号：US17173127

申请日：2021-02-10

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Matthew B. Smittle

IPC: G06F11/00 ,  G06F11/36 ,  G06F11/30 ,  G06F11/07 ,  G06F11/14

Abstract: The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.