公开(公告)号：US10242145B1

公开(公告)日：2019-03-26

申请号：US15585607

申请日：2017-05-03

Applicant: Cadence Design Systems, Inc.

Inventor： Harpreet Singh Anand ,  Paul W. Kollaritsch ,  Mohan Kumar Chalamalashatty

IPC: G06F17/50

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain additional aspects, embodiments include a power grid optimizer for optimizing portions of a power grid based on analytics such as QOR analytics, and incrementally updating the power grid to include these optimized portions.