公开(公告)号：US10242145B1

公开(公告)日：2019-03-26

申请号：US15585607

申请日：2017-05-03

Applicant: Cadence Design Systems, Inc.

Inventor： Harpreet Singh Anand ,  Paul W. Kollaritsch ,  Mohan Kumar Chalamalashatty

IPC: G06F17/50

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain additional aspects, embodiments include a power grid optimizer for optimizing portions of a power grid based on analytics such as QOR analytics, and incrementally updating the power grid to include these optimized portions.

公开(公告)号：US09760667B1

公开(公告)日：2017-09-12

申请号：US14320444

申请日：2014-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Oleg Levitsky ,  Paul W. Kollaritsch

IPC: G06F17/50

CPC classification number: G06F17/5059

Abstract: Methods and systems for implementing prototyping and floorplanning for electronic circuit designs are disclosed. The method identifies or generates a representation of a design, modifies or updates the representation by moving a circuit component in the representation. The representation may be characterized in the pre-placement or post-placement stage to determine or identify distance constraints constraining object pairs in the representation. The method performs a timing and/or congestion analysis with distance-based timing information having a spatial dimension rather than timing information having a temporal dimension for the representation of the electronic design. The timing and/or congestion analysis is performed during the circuit component is being moved or shortly after the circuit component has been moved. The results of the timing and/or congestion analysis are provided in an interactive manner or in a batch mode.

公开(公告)号：US10540470B1

公开(公告)日：2020-01-21

申请号：US15585623

申请日：2017-05-03

Applicant: Cadence Design Systems, Inc.

Inventor： Paul W. Kollaritsch

IPC: G06F17/50

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.