公开(公告)号：US11334110B1

公开(公告)日：2022-05-17

申请号：US17164321

申请日：2021-02-01

Applicant: Cadence Design Systems, Inc.

Inventor： Xiaobin Yuan ,  Aida Varzaghani ,  Irina Gavshina ,  Mouna Safi-Harab

IPC: G06F1/10 ,  G06F1/08 ,  H03L7/07

Abstract: In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.

公开(公告)号：US10944397B1

公开(公告)日：2021-03-09

申请号：US16779400

申请日：2020-01-31

Applicant: Cadence Design Systems, Inc.

Inventor： Xiaobin Yuan ,  Dimitri Loizos ,  Hiu Ming Lam ,  Mouna Safi-Harab

IPC: H04B3/00 ,  H03K17/687 ,  H04L25/02 ,  H04B1/04

Abstract: The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.