公开(公告)号：US10546084B1

公开(公告)日：2020-01-28

申请号：US15833332

申请日：2017-12-06

Applicant: Cadence Design Systems, Inc.

Inventor： Nizar Hanna ,  Maayan Ziv ,  Almothana Sarhan ,  Kanwar Pal Singh ,  Rabin Shahav

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also include displaying, at a graphical user interface, the one or more violations in a ranked order.