公开(公告)号：US10546084B1

公开(公告)日：2020-01-28

申请号：US15833332

申请日：2017-12-06

Applicant: Cadence Design Systems, Inc.

Inventor： Nizar Hanna ,  Maayan Ziv ,  Almothana Sarhan ,  Kanwar Pal Singh ,  Rabin Shahav

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also include displaying, at a graphical user interface, the one or more violations in a ranked order.

公开(公告)号：US10769333B1

公开(公告)日：2020-09-08

申请号：US16148203

申请日：2018-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Maayan Ziv ,  Nizar Hanna ,  Sanaa Halloun

IPC: G06F30/3323 ,  G06F30/30

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.

公开(公告)号：US10452798B1

公开(公告)日：2019-10-22

申请号：US15808094

申请日：2017-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Nizar Hanna ,  Habeeb Farah ,  Almothana Sarhan ,  Doron Bustan

IPC: G06F17/50

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing formal verification of at least a portion of the electronic design having an original property. Embodiments may further include analyzing at least one output net bit associated with a check of the electronic design. Embodiments may also include generating a structural observability expression, based upon, at least in part, the at least one output net bit and setting the structural observability expression as a precondition to the original property.

公开(公告)号：US11138355B1

公开(公告)日：2021-10-05

申请号：US17099301

申请日：2020-11-16

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Maayan Ziv ,  Kanwar Pal Singh ,  Nizar Hanna ,  Gasob Mazzawi

IPC: G06F30/327 ,  G06F30/394 ,  G06F30/398 ,  G06F30/333 ,  G06F30/3323 ,  G06F30/3308

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute a root cause search for a selected cover in the subset of covers that are unreachable. The root cause search selectively adds and removes cutpoints to signals in the circuit design to identify a root cause for the selected cover being unreachable. The root cause comprises a signal in the circuit design that is upstream from the selected cover.

公开(公告)号：US10599797B1

公开(公告)日：2020-03-24

申请号：US15832279

申请日：2017-12-05

Applicant: Cadence Design Systems, Inc.

Inventor： Nizar Hanna ,  Kanwar Pal Singh ,  Maayan Ziv ,  Sudeep Kumar Srivastava ,  Tamer Mograbi ,  Sanaa Halloun

IPC: G06F17/50

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing linting analysis using structural and formal methods of at least a portion of the electronic design. Embodiments may also include identifying a plurality of failures from the formal verification and identifying one or more of the plurality of failures as having a similar root cause. Embodiments may include grouping the one or more of the plurality of failures together, wherein grouping is based upon, at least in part, a check type.