公开(公告)号：US10984164B1

公开(公告)日：2021-04-20

申请号：US16661974

申请日：2019-10-23

Applicant: Cadence Design Systems, Inc.

Inventor： Ankur Chaplot ,  Yashu Gupta ,  Nikhil Garg ,  Sachin Shrivastava ,  Michaela Guiney ,  Sankalp Srivastava

IPC: G06F30/392 ,  G06F30/327 ,  G06F30/398 ,  G06F111/04

Abstract: An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.