公开(公告)号：US11435401B1

公开(公告)日：2022-09-06

申请号：US17181486

申请日：2021-02-22

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Santosh Subhaschandra Malagi

IPC: G01R31/3183 ,  G01R31/3181 ,  G06F30/31 ,  G06F30/33

Abstract: A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.

公开(公告)号：US11461520B1

公开(公告)日：2022-10-04

申请号：US17180239

申请日：2021-02-19

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Micahel Swenton ,  Santosh Subhaschandra Malagi

IPC: G06F30/31 ,  G01R31/3183 ,  G06F30/343 ,  G06F30/323 ,  G06F30/333 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3323

Abstract: An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

公开(公告)号：US11429776B1

公开(公告)日：2022-08-30

申请号：US17181470

申请日：2021-02-22

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Santosh Subhaschandra Malagi

IPC: G06F30/398

Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.