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    Diagnosing multicycle faults and/or defects with single cycle ATPG test patterns
    2.
    发明授权
    Diagnosing multicycle faults and/or defects with single cycle ATPG test patterns 有权

    公开(公告)号：US11740284B1

    公开(公告)日：2023-08-29

    申请号：US17366227

    申请日：2021-07-02

    Applicant: Cadence Design Systems, Inc.

    Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

    IPC: G01R31/3177 ,  G06F30/392 ,  G06F30/31

    CPC classification number: G01R31/3177 ,  G06F30/392 ,  G06F30/31

    Abstract: An integrated circuit (IC) test engine generates single cycle test patterns for testing for candidate faults and/or defects of a first set of static faults and/or defects of an IC design. A diagnostics engine receives single cycle test result data characterizing application of the single cycle test patterns to a fabricated IC chip based on the IC design and fault-simulates a subset of the single cycle test patterns against a fault model that includes multicycle faults and/or defects utilizing sim-shifting to diagnose a second set of static faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns. The diagnostics engine further scores candidate faults and/or defects in the first set of static faults and/or defects and the second set of static faults and/or defects for applicable test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

    Fault rules files for testing an IC chip
    3.
    发明授权
    Fault rules files for testing an IC chip 有权

    公开(公告)号：US11429776B1

    公开(公告)日：2022-08-30

    申请号：US17181470

    申请日：2021-02-22

    Applicant: Cadence Design Systems, Inc.

    Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Santosh Subhaschandra Malagi

    IPC: G06F30/398

    Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

    Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip
    4.
    发明授权
    Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip 有权

    公开(公告)号：US11435401B1

    公开(公告)日：2022-09-06

    申请号：US17181486

    申请日：2021-02-22

    Applicant: Cadence Design Systems, Inc.

    Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Santosh Subhaschandra Malagi

    IPC: G01R31/3183 ,  G01R31/3181 ,  G06F30/31 ,  G06F30/33

    Abstract: A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.

    System and method for diagnosing failure locations in electronic circuits
    6.
    发明授权
    System and method for diagnosing failure locations in electronic circuits 有权

    公开(公告)号：US09864004B1

    公开(公告)日：2018-01-09

    申请号：US15073001

    申请日：2016-03-17

    Applicant: Cadence Design Systems, Inc.

    Inventor： Sameer Chakravarthy Chillarige ,  Brion L. Keller ,  Joseph Michael Swenton ,  Sharjinder Singh ,  Anil Malik

    IPC: G06F11/22 ,  G06F17/50 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31703 ,  G01R31/31908 ,  G06F11/00

    Abstract: Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.

    Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip
    7.
    发明授权
    Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip 有权

    公开(公告)号：US11893336B1

    公开(公告)日：2024-02-06

    申请号：US17499414

    申请日：2021-10-12

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

    IPC: G06F30/398 ,  G06F119/18 ,  G06F119/12

    CPC classification number: G06F30/398 ,  G06F2119/12 ,  G06F2119/18

    Abstract: An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.

    System and method performing scan chain diagnosis of an electronic design
    9.
    发明授权
    System and method performing scan chain diagnosis of an electronic design 有权

    公开(公告)号：US10180457B1

    公开(公告)日：2019-01-15

    申请号：US15062013

    申请日：2016-03-04

    Applicant: Cadence Design Systems, Inc.

    Inventor： Sameer Chakravarthy Chillarige ,  Sharjinder Singh ,  Anil Malik ,  Joseph Michael Swenton

    IPC: G01R31/317 ,  G01R31/3177 ,  G06F17/50 ,  G01R31/00 ,  G01R31/311

    Abstract: The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

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