公开(公告)号：US11341002B1

公开(公告)日：2022-05-24

申请号：US17061348

申请日：2020-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Mehran Mohammadi Izad ,  Aida Varzaghani ,  Bardia Bozorgzadeh ,  Stefanos Sidiropoulos

IPC: G06F1/10 ,  G06F11/16

Abstract: An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.