公开(公告)号：US11632119B1

公开(公告)日：2023-04-18

申请号：US17727922

申请日：2022-04-25

Applicant: Cadence Design Systems, Inc.

Inventor： Sudipta Sarkar ,  Dimitrios Loizos ,  Mehran Mohammadi Izad ,  Paul Lee ,  Steven Elliott Mikes ,  Manohar Bhavsar Nagaraju

IPC: H03K23/00 ,  H03L7/197 ,  H03K23/66 ,  H03K23/58 ,  H03K23/48

Abstract: Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

公开(公告)号：US11341002B1

公开(公告)日：2022-05-24

申请号：US17061348

申请日：2020-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Mehran Mohammadi Izad ,  Aida Varzaghani ,  Bardia Bozorgzadeh ,  Stefanos Sidiropoulos

IPC: G06F1/10 ,  G06F11/16

Abstract: An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.