公开(公告)号：US10599797B1

公开(公告)日：2020-03-24

申请号：US15832279

申请日：2017-12-05

Applicant: Cadence Design Systems, Inc.

Inventor： Nizar Hanna ,  Kanwar Pal Singh ,  Maayan Ziv ,  Sudeep Kumar Srivastava ,  Tamer Mograbi ,  Sanaa Halloun

IPC: G06F17/50

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing linting analysis using structural and formal methods of at least a portion of the electronic design. Embodiments may also include identifying a plurality of failures from the formal verification and identifying one or more of the plurality of failures as having a similar root cause. Embodiments may include grouping the one or more of the plurality of failures together, wherein grouping is based upon, at least in part, a check type.