公开(公告)号：US20230350805A1

公开(公告)日：2023-11-02

申请号：US17661427

申请日：2022-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Thomas M. Wicki

IPC: G06F12/0837 ,  G06F12/0877 ,  G06F9/30

CPC classification number: G06F12/0837 ,  G06F12/0877 ,  G06F9/30138

Abstract: Techniques are disclosed relating to an apparatus that includes a plurality of memory access control registers that are programmable with respective address ranges within an address space. The apparatus further includes a memory access circuit configured to receive a command for performing a memory access, the command specifying an address corresponding to a location in a memory circuit. In response to the address being located within an address range of a particular one of the plurality of memory access control registers, the memory access circuit is configured to perform the command using override memory parameters that have been programmed into the particular memory access control register instead of a default set of attributes for the address space.