公开(公告)号：US11507414B2

公开(公告)日：2022-11-22

申请号：US17173108

申请日：2021-02-10

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Thomas Martin Wicki ,  Jama Ismail Barreh

IPC: G06F13/40 ,  G06F9/48 ,  G06F9/30

Abstract: A circuit for fast interrupt handling is disclosed. An apparatus includes a processor circuit having an execution pipeline and a table configured to store a plurality of pointers that correspond to interrupt routines stored in a memory circuit. The apparatus further includes an interrupt redirect circuit configured to receive a plurality of interrupt requests. The interrupt redirect circuit may select a first interrupt request among a plurality of interrupt requests of a first type. The interrupt redirect circuit retrieves a pointer from the table using information associated with the request. Using the pointer, the execution pipeline retrieves first program instruction from the memory circuit to execute a particular interrupt routine.