公开(公告)号：US10423744B1

公开(公告)日：2019-09-24

申请号：US14607914

申请日：2015-01-28

Applicant: Cadence Design Systems, Inc.

Inventor： Joel Reuben Phillips ,  Jun Meng ,  Yunbo Pang

IPC: G06F17/50

Abstract: A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.