公开(公告)号：US12141233B1

公开(公告)日：2024-11-12

申请号：US16587790

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Marco Tony Lloyd Kassis ,  Mina Adel Aziz Farhan ,  Joel Reuben Phillips

IPC: G06F18/214 ,  G06F17/12 ,  G06F17/14 ,  G06N20/00

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

公开(公告)号：US10423744B1

公开(公告)日：2019-09-24

申请号：US14607914

申请日：2015-01-28

Applicant: Cadence Design Systems, Inc.

Inventor： Joel Reuben Phillips ,  Jun Meng ,  Yunbo Pang

IPC: G06F17/50

Abstract: A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.