公开(公告)号：US5809291A

公开(公告)日：1998-09-15

申请号：US802369

申请日：1997-02-19

申请人： Carlos Munoz-Bustamante ,  Jerry William Pearce

发明人： Carlos Munoz-Bustamante ,  Jerry William Pearce

IPC分类号： G06F1/08 ,  H03L7/183 ,  G06F1/12

CPC分类号： G06F1/08 ,  H03L7/183

摘要： An extended PCI bus (100) accepts both standard 33 MHz (101-102) and extended 66 MHz (103-104) PCI I/O devices, and permits the intermixing and interoperability of both types of devices on the same bus. Each extended 66 MHz initiator device (103) includes a target memory (205) that is programmed at boot up to include a list of address ranges of all extended 66 MHz devices. Each extended 66 MHz device includes a clock multiplier (202) that generates an internal 66 MHz clock signal by doubling the 33 MHz bus clock frequency. This clock multiplier may be in the form of a simple edge detecting frequency doubler (FIG. 4), or a phase locked loop (FIG. 5) that can also provide for phase adjustments to alter the skew between the bus and internal clocks. To transfer data between two extended 66 MHz devices, an extended initiator device sends, during the address/control phase of the bus cycle, a fast read or write command to the extended target device over the C/BE lines of the bus. Subsequently during the data phase of the bus cycle, data is transferred over the bus at the 66 MHz rate using the 66 MHz internal clock signals.

摘要翻译： 扩展PCI总线（100）接受标准33 MHz（101-102）和扩展66 MHz（103-104）PCI I / O设备，并允许两种类型的设备在同一总线上的混合和互操作性。 每个扩展的66MHz启动器设备（103）包括目标存储器（205），其在引导时被编程以包括所有扩展的66MHz设备的地址范围的列表。 每个扩展的66 MHz器件包括一个时钟乘法器（202），通过将33 MHz总线时钟频率加倍来产生内部66 MHz时钟信号。 该时钟倍频器可以是简单边缘检测倍频器（图4）或锁相环（图5）的形式，其也可以提供相位调整以改变总线与内部时钟之间的偏斜。 为了在两个扩展的66 MHz器件之间传输数据，扩展启动器设备在总线周期的地址/控制阶段，通过总线的C / BE线向扩展目标器件发送快速读或写命令。 随后在总线周期的数据阶段，数据通过总线以66 MHz的速率通过66 MHz内部时钟信号传输。

公开(公告)号：US06820182B1

公开(公告)日：2004-11-16

申请号：US09691533

申请日：2000-10-18

申请人： Charles David Bauman ,  Richard Bealkowski ,  Thomas J Clement ,  Jerry William Pearce ,  Michael Robert Turner

发明人： Charles David Bauman ,  Richard Bealkowski ,  Thomas J Clement ,  Jerry William Pearce ,  Michael Robert Turner

IPC分类号： G06F1200

CPC分类号： G06F11/2069 ,  G06F12/023 ,  G06F2212/401 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A memory exhaustion condition is handled in a data processing system having first and second regions of physical memory. The memory exhaustion condition is detected while the second region is mirroring at least part of the first region. In response to the memory exhaustion condition, memory mirroring is at least partially deactivated and at least part of the second region is utilized to augment the first region, such that the memory exhaustion condition is eliminated. In an illustrative embodiment, the data processing system compresses real memory into the first region of physical memory, and the memory exhaustion condition arises when the first region lacks sufficient available capacity to accommodate current requirements for real memory. The memory exhaustion condition is eliminated by compressing at least part of the real memory into the second region.

摘要翻译： 在具有物理存储器的第一和第二区域的数据处理系统中处理存储器耗尽条件。 当第二区域镜像第一区域的至少一部分时，检测存储器耗尽条件。 响应于存储器耗尽条件，存储器镜像至少部分被去激活，并且第二区域的至少一部分被用于增加第一区域，从而消除了存储器耗尽条件。 在说明性实施例中，数据处理系统将实际存储器压缩到物理存储器的第一区域中，并且当第一区域缺少足够的可用容量以适应对真实存储器的当前需求时，出现存储器耗尽状况。 通过将至少部分实际存储器压缩到第二区域来消除存储器耗尽条件。