公开(公告)号：US4315312A

公开(公告)日：1982-02-09

申请号：US105186

申请日：1979-12-19

Applicant: Carson T. Schmidt

Inventor： Carson T. Schmidt

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0864 ,  G06F2212/601

Abstract: A cache memory has a data buffer for storing blocks of data from a main memory and an index for storing main memory addresses associated with the data blocks in the data buffer. The size of the blocks of data stored in the data buffer can be varied in order to increase the "hit ratio" of the cache memory. The index is a set associative memory and bits provided to an address input of the index are selectively inhibited by an address inhibit circuit when the size of the data blocks in the data buffer is to be varied. A block size register stores block size information that is provided to the address inhibit circuit. The block size information is also provided to a fetch generate counter and a fetch return counter that control the number of words transferred as a block from the main memory to the cache memory.

Abstract translation: 高速缓冲存储器具有用于存储来自主存储器的数据块的数据缓冲器和用于存储与数据缓冲器中的数据块相关联的主存储器地址的索引。 可以改变存储在数据缓冲器中的数据块的大小，以便增加高速缓冲存储器的“命中率”。 当数据缓冲器中的数据块的大小要变化时，索引是设置的相关存储器，并且提供给索引的地址输入的位被地址禁止电路选择性地禁止。 块大小寄存器存储提供给地址禁止电路的块大小信息。 块大小信息还提供给获取生成计数器和提取返回计数器，该计数器将从主存储器传送的字数量控制到高速缓存存储器。

公开(公告)号：US4272829A

公开(公告)日：1981-06-09

申请号：US865457

申请日：1977-12-29

Applicant: Carson T. Schmidt ,  William P. Ward ,  Rocky M. Y. Young

Inventor： Carson T. Schmidt ,  William P. Ward ,  Rocky M. Y. Young

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/405

Abstract: A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.

Abstract translation: 一种能够用于计算机的各种组件的寄存器电路。 寄存器电路包括两个寄存器和逻辑电路，其使多个数据总线能够以各种配置选择性地连接到寄存器的数据输入和输出。 在示出使用发射极耦合逻辑构造的寄存器电路的实施例中，时钟电路产生用于选择要连接到每个寄存器的输入的数据总线的时钟信号。 每个寄存器包括多个主从触发器，其接收来自时钟电路的时钟信号，并且响应于这些信号将触发器可操作地连接到所选择的总线或总线。

公开(公告)号：US4646312A

公开(公告)日：1987-02-24

申请号：US681347

申请日：1984-12-13

Applicant: Timothy G. Goldsbury ,  Carson T. Schmidt

Inventor： Timothy G. Goldsbury ,  Carson T. Schmidt

IPC: H03M13/00 ,  G06F11/00 ,  H03M13/19

CPC classification number: H03M13/19 ,  G06F11/008

Abstract: An error detection and correction apparatus including a transmission bus for transmitting multi-bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code technique. Parity generators are connected to the bus for receiving the bits of the data signals and selected bits of the error correction code signals in accordance with the modified Hamming code technique for determining if a single bit error exists in the data. A two-state comparison gate is connected to the parity generators which has a first state if a single bit error does exist, and a second state if a single bit error does not exist. A separate error detection and correction circuit is provided to detect and correct any single bit errors in the data on the transmission bus. The two-state comparison gate is reset to its second state after the separate error detection and correction circuit corrects any single bit error in the data.

Abstract translation: 一种错误检测和校正装置，包括用于发送多位数据信号的传输总线和根据修改的汉明码技术响应于多位数据信号产生的多位纠错码信号。 奇偶校验发生器连接到总线，用于根据用于确定数据中是否存在单个位错误的修改的汉明码技术接收数据信号的位和纠错码信号的选定位。 两状态比较门连接到奇偶校验生成器，如果存在单个位错误则具有第一状态，如果不存在单个位错误则连接到第二状态。 提供单独的错误检测和校正电路来检测和校正传输总线上的数据中的任何单个位错误。 在单独的错误检测和校正电路校正数据中的任何单个位错误之后，两状态比较门复位到第二状态。

公开(公告)号：US4747044A

公开(公告)日：1988-05-24

申请号：US643512

申请日：1984-08-23

Applicant: Carson T. Schmidt ,  Chenyu Chao ,  Gregory D. Brinson ,  Jerrold L. Allen ,  Barry L. Loges ,  Timothy G. Goldsbury ,  Robert O. Gunderson ,  Jerry K. Herreweyers

Inventor： Carson T. Schmidt ,  Chenyu Chao ,  Gregory D. Brinson ,  Jerrold L. Allen ,  Barry L. Loges ,  Timothy G. Goldsbury ,  Robert O. Gunderson ,  Jerry K. Herreweyers

IPC: G06F9/22 ,  G06F12/10 ,  G06F13/08

CPC classification number: G06F9/22 ,  G06F12/1063

Abstract: A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.

Abstract translation: 一种数据处理系统，包括用于存储数据和可直接执行的微指令的可寻址主存储器，以及具有数据接口终端和指令终端的中央处理芯片。 处理器存储器总线连接在主可寻址存储器和中央处理芯片数据接口终端之间。 指令总线连接在中央处理芯片指令终端和可寻址存储器之间。 可寻址主存储器中的可直接执行的微指令通过包括连接到处理器存储器总线和指令总线的指令地址电路的装置从主存储器中取出。 指令地址电路包括用于从指令总线接收虚拟地址的一部分的虚拟地址寄存器电路和来自处理器存储器总线的所述虚拟地址的一部分。 指令地址电路中的虚拟到实际的转换电路将虚拟地址寄存器中的虚拟地址转换为可寻址存储器中的可实际地址，可从中获取可执行的微指令。