公开(公告)号：US20200097442A1

公开(公告)日：2020-03-26

申请号：US16241085

申请日：2019-01-07

Applicant: Ceva D.S.P. Ltd.

Inventor： Jeffrey Allan (Alon) Jacob (Yaakov) ,  Roni M. Sadeh

IPC: G06F15/80 ,  G06F9/30

Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

公开(公告)号：US10402196B2

公开(公告)日：2019-09-03

申请号：US14708767

申请日：2015-05-11

Applicant: Ceva D.S.P. Ltd.

Inventor： Roni M. Sadeh ,  Noam Dvoretzki

IPC: G06F9/30

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

公开(公告)号：US10831702B2

公开(公告)日：2020-11-10

申请号：US16241085

申请日：2019-01-07

Applicant: Ceva D.S.P. Ltd.

Inventor： Jeffrey Allan (Alon) Jacob (Yaakov) ,  Roni M. Sadeh

IPC: G06F9/30 ,  G06F15/80

Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.