公开(公告)号：US10306516B2

公开(公告)日：2019-05-28

申请号：US15438823

申请日：2017-02-22

Applicant: Ceva D.S.P. Ltd.

Inventor： David Levy

IPC: H04W28/22 ,  H04L29/06 ,  H03M13/27 ,  H03M13/29 ,  H03M13/00 ,  H04L1/00

Abstract: A method and a logic circuit for rate matching for three equally sized bit streams, including: prepending each of the bit streams with null bits; permuting the first two bit streams according to a first permutation pattern; permuting the third bit stream based on the first permutation pattern; transposing the three bit streams; shuffling the second and third bit streams; removing the null bits from the first bit stream and from the shuffled bit stream, wherein location of the null bits in the first bit stream is based only on a number of prepended null bits and the first permutation pattern and location of the null bits in the shuffled bit stream is based only on the number of prepended null bits, the first permutation pattern, and a null index related to the number of prepended null bits; and generating a combined bit stream from the three bit streams.

公开(公告)号：US10169040B2

公开(公告)日：2019-01-01

申请号：US15352598

申请日：2016-11-16

Applicant: Ceva D.S.P. Ltd.

Inventor： Hagay Rozin ,  Jeffery Allan (Alon) Jacob (Yaakov)

IPC: G06F9/30 ,  G06F17/10

Abstract: A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.

公开(公告)号：US09977601B2

公开(公告)日：2018-05-22

申请号：US15073103

申请日：2016-03-17

Applicant: Ceva D.S.P. Ltd.

Inventor： Hagay Rozin ,  Jeffrey Allan (Alon) Jacob (Yaakov)

IPC: G06F3/06 ,  H03H17/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  H03H17/0223 ,  H03H17/06

Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

公开(公告)号：US20180136935A1

公开(公告)日：2018-05-17

申请号：US15352598

申请日：2016-11-16

Applicant: Ceva D.S.P. Ltd.

Inventor： Hagay ROZIN ,  Jeffery Allan (Alon) JACOB (YAAKOV)

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30116 ,  G06F9/30134

Abstract: A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.

公开(公告)号：US20170255572A1

公开(公告)日：2017-09-07

申请号：US15062436

申请日：2016-03-07

Applicant: Ceva D.S.P. Ltd.

Inventor： Amos ROHE ,  Roni M. SADEH

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F12/1483 ,  G06F12/0826 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0875 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1052 ,  G06F2212/6026 ,  G06F2212/622 ,  G06T1/60

Abstract: A system and method for preventing cache contention for a cache including a plurality of ways and a separate port for each way, the method including: obtaining, in a core of a processor, a multidimensional coefficient array of a multidimensional filter, and pointers to data elements from a plurality of rows of a multidimensional data array, and loading the plurality of rows into the cache, where each row is stored in a different way of the cache.

公开(公告)号：US20150222457A1

公开(公告)日：2015-08-06

申请号：US14341869

申请日：2014-07-28

Applicant: Ceva D.S.P. Ltd.

Inventor： Zeev KAPLAN ,  Noam Dvoretzki ,  Eitan Hai

IPC: H04L25/03 ,  H04B7/02

CPC classification number: H04L25/03242 ,  H04B7/02 ,  H04L25/03191 ,  H04L2025/03426

Abstract: A method and system for soft output multiple-input-multiple-output (MIMO) decoding may include generating a tree-graph based on: MIMO rank, number of bits per layer, and type of modulation, wherein the tree-graph comprises a root node, leaf nodes, nodes, and branches connecting the nodes; performing sphere decoding by determining a radius covering a subset of nodes within said tree-graph; managing, based on the sphere decoding, tables comprising metrics and counter metrics usable for log likelihood ratio (LLR) generation; predicting, based on a specified prediction scheme, counter metrics for paths in the tree-graph that comprise nodes and branches out of the determined radius; and updating the tables comprising the counter metrics with the predicted counter metric, in a case that the predicted counter metrics are better in maximum likelihood terms than the determined counter metrics.

Abstract translation: 用于软输出多输入多输出（MIMO）解码的方法和系统可以包括：基于：MIMO秩，每层的比特数和调制类型来生成树图，其中树图包括根 节点，叶节点，节点和连接节点的分支; 通过确定覆盖所述树形图中的节点子集的半径来执行球体解码; 基于球体解码管理包括可用于对数似然比（LLR）生成的度量和计数度量的表; 基于指定的预测方案来预测包括确定半径之外的节点和分支的树图中的路径的计数度量; 以及在所述预测计数器度量与所确定的计数器度量相比最大似然项更好的情况下，更新包括具有所述预测计数器度量的所述计数器度量的表。

公开(公告)号：US20250044401A1

公开(公告)日：2025-02-06

申请号：US18361973

申请日：2023-07-31

Applicant: Ceva D.S.P. Ltd.

Inventor： Zeev KAPLAN

IPC: G01S7/02

Abstract: A method and system for finding a Kth element in a series of values, including: organizing the series of values in a PDF by counting a number of occurrences of each value of the series of values; organizing the series of values in a CDF that includes adjacent bins of ranges of values, by counting for each bin an accumulated number of occurrences of values of the series of values up to a bin index of that bin; finding in the CDF a bin for which the associated accumulated number of occurrences is a largest accumulated number of occurrences among the accumulated number of occurrences that is smaller than K; and finding the Kth largest element by searching the PDF for the Kth largest element, starting from the found bin index.

公开(公告)号：US12057986B2

公开(公告)日：2024-08-06

申请号：US17679944

申请日：2022-02-24

Applicant: Ceva D.S.P. Ltd.

Inventor： Tomer Yablonka ,  Guy Keshet ,  Zeev Kaplan

IPC: H04W4/00 ,  H04L1/00 ,  H04L25/06 ,  H04L27/34

CPC classification number: H04L27/3405 ,  H04L1/0054 ,  H04L25/061

Abstract: A method and system for performing quadrature amplitude modulation (QAM) decoding of a received signal includes finding for each layer a region in a first constellation diagram of the received signal, the region including a portion of the first constellation diagram, the portion having the same size of a second constellation diagram, and a first constellation order of the received signal is higher than a second constellation order of the second constellation diagram; and, for each layer: finding a first portion of bits based on bits that are constant among constellation points located in the region of the layer; decoding the received signal using a QAM decoder having the second constellation order to obtain a second portion of bits; adjusting the second portion of bits based on the region of the layer; and merging the first portion of bits with the second portion of bits to obtain a decoded symbol.

公开(公告)号：US20230269124A1

公开(公告)日：2023-08-24

申请号：US17679944

申请日：2022-02-24

Applicant: Ceva D.S.P. Ltd.

Inventor： Tomer YABLONKA ,  Guy KESHET ,  Zeev KAPLAN

IPC: H04L27/34 ,  H04L25/06 ,  H04L1/00

CPC classification number: H04L27/3405 ,  H04L25/061 ,  H04L1/0054

Abstract: A method and system for performing quadrature amplitude modulation (QAM) decoding of a received signal includes finding for each layer a region in a first constellation diagram of the received signal, the region including a portion of the first constellation diagram, the portion having the same size of a second constellation diagram, and a first constellation order of the received signal is higher than a second constellation order of the second constellation diagram; and, for each layer: finding a first portion of bits based on bits that are constant among constellation points located in the region of the layer; decoding the received signal using a QAM decoder having the second constellation order to obtain a second portion of bits; adjusting the second portion of bits based on the region of the layer; and merging the first portion of bits with the second portion of bits to obtain a decoded symbol.

公开(公告)号：US11228359B1

公开(公告)日：2022-01-18

申请号：US17141398

申请日：2021-01-05

Applicant: Ceva D.S.P. Ltd.

Inventor： Tomer Yablonka

IPC: H04B7/08 ,  H04B17/20 ,  H04B1/06 ,  H04B7/0413

Abstract: A method and system for performing Maximum Likelihood Detector (MLD) preprocessing in a Multiple-Input Multiple-Output (MIMO) communication system, the method including, obtaining a received signal Y a corresponding channel matrix H and a vector of noise samples n; calculating a whitening filter L−H; whitening a channel matrix H; selecting one of a first calculation or a second calculation, based on estimated complexity of the calculations; and performing preprocessing of the received signal using the selected calculation. The first calculation includes: whitening the received signal and performing a Cordic based QR decomposition to the whitened channel matrix {tilde over (H)} and the whitened received signal {tilde over (Y)} to obtain triangular matrix R and Y=QHL−HY. The second calculation includes: performing a Cordic based QR decomposition to the whitened channel matrix {tilde over (H)} and the whitening filter L−H to obtain triangular matrix R and QHL−H, and multiplying the received signal Y by QHL−H to obtain Y=QHL−HY.