公开(公告)号：US08279687B2

公开(公告)日：2012-10-02

申请号：US12779608

申请日：2010-05-13

申请人： Chad A. Adams ,  George M. Braceras ,  Daniel M Nelson ,  Harold Pilo ,  Vinod Ramadurai

发明人： Chad A. Adams ,  George M. Braceras ,  Daniel M Nelson ,  Harold Pilo ,  Vinod Ramadurai

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C11/419

摘要： A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.

摘要翻译： 已经发现降低的位线预充电水平增加了SRAM Beta比率，从而提高了稳定裕度。 预充电电平也提供给Sense放大器，写入驱动器和源电压用于控制信号。 在读出放大器中，较低的预充电电压通过以增加的超速驱动来操作全局数据线驱动器来补偿位单元中的性能损失。 在写入驱动器中，降低的电压提高了位线放电速率，提高了负升压写入辅助的效率，并降低了来自负升压电路的写入通路中的晶体管的可靠性暴露。