公开(公告)号：US07779393B1

公开(公告)日：2010-08-17

申请号：US11137755

申请日：2005-05-25

申请人： Chaiyasit Manovit ,  Sudheendra G. Hangal ,  Robert E. Cypher

发明人： Chaiyasit Manovit ,  Sudheendra G. Hangal ,  Robert E. Cypher

IPC分类号： G06F9/44 ,  G06F12/00 ,  G06F9/45

CPC分类号： G06F11/2242 ,  G06F12/0815

摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model.

摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否符合事件的有效排序 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。

公开(公告)号：US20080288834A1

公开(公告)日：2008-11-20

申请号：US11750671

申请日：2007-05-18

申请人： Chaiyasit Manovit ,  Sudheendra G. Hangal

发明人： Chaiyasit Manovit ,  Sudheendra G. Hangal

IPC分类号： G11C29/08 ,  G06F9/44

CPC分类号： G06F11/3612 ,  G06F11/28

摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.

摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否与事件的有效排序相对应 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。 此外，可以执行回溯搜索以在存在这样的排序的情况下找到有效的排序，或者显示不存在，并且因此确认结果是否符合给定的存储器一致性模型。

公开(公告)号：US07814378B2

公开(公告)日：2010-10-12

申请号：US11750671

申请日：2007-05-18

申请人： Chaiyasit Manovit ,  Sudheendra G. Hangal

发明人： Chaiyasit Manovit ,  Sudheendra G. Hangal

IPC分类号： G11C29/00 ,  G06F11/00 ,  G06F12/00

CPC分类号： G06F11/3612 ,  G06F11/28

摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.

摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否符合事件的有效排序 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。 此外，可以执行回溯搜索以在存在这样的排序的情况下找到有效的排序，或者显示不存在，并且因此确认结果是否符合给定的存储器一致性模型。

公开(公告)号：US07689399B1

公开(公告)日：2010-03-30

申请号：US10931727

申请日：2004-08-31

申请人： Sudheendra G. Hangal ,  Naveen Chandra

发明人： Sudheendra G. Hangal ,  Naveen Chandra

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for automatic extraction of design properties of a hardware design, is provided. The method includes running a hardware design simulation to generate simulation results for the hardware design. The simulation results are then analyzed to extract properties. The extracted properties can be a powerful tool for the design engineers and the test-writers to learn more about the functional coverage of the test suites.

摘要翻译： 提供了一种自动提取硬件设计的设计特性的方法。 该方法包括运行硬件设计仿真，以生成硬件设计的仿真结果。 然后分析模拟结果以提取属性。 提取的属性可以是设计工程师和测试人员更多地了解测试套件的功能覆盖的强大工具。