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1.发明授权System and method for efficient verification of memory consistency model compliance 有权用于有效验证内存一致性模型符合性的系统和方法公开(公告)号：US07779393B1
公开(公告)日：2010-08-17
申请号：US11137755
申请日：2005-05-25
CPC分类号： G06F11/2242 , G06F12/0815
摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model.
摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否符合事件的有效排序 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。
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公开(公告)号：US20080288834A1
公开(公告)日：2008-11-20
申请号：US11750671
申请日：2007-05-18
CPC分类号： G06F11/3612 , G06F11/28
摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.
摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否与事件的有效排序相对应 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。 此外，可以执行回溯搜索以在存在这样的排序的情况下找到有效的排序，或者显示不存在，并且因此确认结果是否符合给定的存储器一致性模型。
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公开(公告)号：US07814378B2
公开(公告)日：2010-10-12
申请号：US11750671
申请日：2007-05-18
CPC分类号： G06F11/3612 , G06F11/28
摘要： A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.
摘要翻译： 用于有效地验证与存储器一致性模型的一致性的系统包括测试模块和分析模块。 测试模块可以在测试平台上协调多线程测试程序的执行。 如果测试平台提供了在共享存储器位置处执行来自多个处理元件的写入的顺序的指示，则分析模块可以使用第一组规则来验证执行结果是否符合事件的有效排序 到内存一致性模型。 如果测试平台不提供写入顺序的指示，则分析模块可以使用第二组规则来验证与存储器一致性模型的一致性。 此外，可以执行回溯搜索以在存在这样的排序的情况下找到有效的排序，或者显示不存在，并且因此确认结果是否符合给定的存储器一致性模型。
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4.发明授权Method and system for verifying power-optimized electronic designs using equivalency checking 有权使用等效性检查验证功率优化电子设计的方法和系统公开(公告)号：US08099703B1
公开(公告)日：2012-01-17
申请号：US12325976
申请日：2008-12-01
CPC分类号： G06F17/504 , G06F2217/78
摘要： Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications. The equivalency between the golden design and the power optimized design can then be verified by checking the golden design and the first design transformation, and then by checking between each pair of the plurality of intermediate design transformations, and finally by checking the last design transformation and the power optimized design.
摘要翻译： 本发明的实施例提供了使用组合等价性检查来验证功率优化设计的功能等同性及其原始的，未优化的设计（称为黄金设计）的方法和系统。 由于一些固有的限制，使得组合等价检查器不能在单个步骤中证明两个设计的等同性，引入了一系列中间设计变换。 这些变换取决于从黄金设计生成功率优化设计中使用的技术，并且可以以提供必要结构来指定整套有效结构修改的变换语言一般性地描述。 然后通过检查黄金设计和第一次设计变换，然后通过检查每对多个中间设计变换之间的检验，最后通过检查最后的设计变换和 电源优化设计。
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公开(公告)号：US08423935B1
公开(公告)日：2013-04-16
申请号：US13035767
申请日：2011-02-25
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.
摘要翻译： 用于验证集成电路的设计和使用基于输出的时钟门控的对应时钟门控设计之间的功能等同性的方法的一个实施例包括选择设计中的第一多个内部状态元素中的第一个和相应的第一个 在时钟门控设计中的第二多个内部状态元件的第一多个内部状态元件中的第一多个内部状态元件的输入到第一多个内部状态元素中的第一个内部状态元素的输入， 状态元素用作第二比较点，并且将设计与第一比较点和第二比较点处的时钟门控设计进行比较，并且生成将第一比较点和第二比较点识别为的测试台 一套比较点。
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公开(公告)号：US08219946B1
公开(公告)日：2012-07-10
申请号：US12835638
申请日：2010-07-13
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.
摘要翻译： 在一个实施例中，提供了一种用于产生用于电路设计模型的时钟选通电路的方法。 确定电路设计网表中每个门元件的路径敏感度的布尔表达式。 对于每个门元件，确定路径敏化的布尔表达式与一个或多个后续门的可观察性条件的分离的布尔表达式的结合以产生中间布尔表达式。 中间布尔表达式被反向重新定时以产生每个门元件的可观察性条件的各自的布尔表达式。 实现实现多个互连门元件中的一个或多个的可观察性条件的相应布尔表达式的时钟选通电路被生成并并入电路设计模型中。
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7.发明申请公开(公告)号：US20100122038A1
公开(公告)日：2010-05-13
申请号：US12266753
申请日：2008-11-07
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F9/528 , G06F12/0842
摘要： Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.
摘要翻译： 公开了允许在执行前进微处理器中改进投机成功的方法和装置。 在一些实施例中，该方法可以包括在执行程序代码的第二线程时推测性地执行程序代码的第一线程，确定加载请求是否可从高速缓存器内的高速缓存线路服务，并且在负载 请求可从高速缓存行服务，将第一指示符位与高速缓存行相关联。 该方法还可以包括确定与第一指示符位相关联的高速缓存行是否已被驱逐，以及在高速缓存行被驱逐的情况下，允许第一线程的推测性执行继续。
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公开(公告)号：US08898401B2
公开(公告)日：2014-11-25
申请号：US12266753
申请日：2008-11-07
CPC分类号： G06F12/127 , G06F9/528 , G06F12/0842
摘要： Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.
摘要翻译： 公开了允许在执行前进微处理器中改进投机成功的方法和装置。 在一些实施例中，该方法可以包括在执行程序代码的第二线程时推测性地执行程序代码的第一线程，确定加载请求是否可从高速缓存器内的高速缓存线路服务，并且在负载 请求可从高速缓存行服务，将第一指示符位与高速缓存行相关联。 该方法还可以包括确定与第一指示符位相关联的高速缓存行是否已被驱逐，以及在高速缓存行被驱逐的情况下，允许第一线程的推测性执行继续。
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9.发明授权Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis 有权通过使用前馈静态输入分析对数字集成电路进行时钟门控的方法和装置公开(公告)号：US07746116B1
公开(公告)日：2010-06-29
申请号：US12356797
申请日：2009-01-21
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.
摘要翻译： 本发明的一个方面涉及一种包括第一存储元件和第一时钟门控元件的器件，其中第一存储元件的数据输入耦合到组合逻辑（CL）元件的输出，其中第一存储元件是 利用第一时钟门控元件对第一时钟门控元件进行时钟门控，以使用第一时钟使能信号来产生用于第一存储元件的时钟信号，其中产生第一时钟使能信号以在第一时钟门控元件中的每个时钟门控元件 当CL元件的至少一个控制输入中的每一个处于第一静止诱导条件时，相对于时钟信号，CL元件的至少一个数据输入处于第二静态诱导条件。
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10.发明授权公开(公告)号：US06892286B2
公开(公告)日：2005-05-10
申请号：US10261157
申请日：2002-09-30
CPC分类号： G06F12/0815 , G06F2212/1032
摘要： A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.
摘要翻译： 用于验证共享存储器多处理器计算机系统的存储器一致性模型的系统和方法产生在处理器上运行的随机指令，保存指令运行的结果，并且如果结果下降，则分析结果以检测存储器子系统错误 在可能结果的空间之外与记忆一致性模型一致。 通过唯一地识别存储位置的结果来确定结果的优先关系，每个结果是不同的，以允许将读取结果值与创建读取结果值的指令相关联。 当检测到指示与内存一致性模型规则不一致的结果的循环时，具有静态，直接和派生边的优先图确定错误。
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