公开(公告)号：US6001696A

公开(公告)日：1999-12-14

申请号：US52453

申请日：1998-03-31

申请人： Chang-gyu Kim ,  Min-su Baek ,  Ji-hyun Choi

发明人： Chang-gyu Kim ,  Min-su Baek ,  Ji-hyun Choi

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.

摘要翻译： 用于集成电路的隔离方法使用绝缘层的等离子体化学气相沉积，然后剥离以去除绝缘层的至少一部分。 特别地，在集成电路基板上形成剥离层。 在剥离层下方的剥离层和集成电路基板被蚀刻以在集成电路基板中形成沟槽。 沟槽限定在沟槽的一侧上的第一区域和比沟槽另一侧上的第一区域窄的第二区域。 然后进行等离子体化学气相沉积以在第一区域和第二区域上形成填充沟槽的绝缘层，第一区域上的绝缘层比第二区域厚。 然后蚀刻绝缘层以暴露第二区域中的剥离层。 然后将剥离层从第一区域提起。 如此形成的绝缘沟槽可以具有改进的隔离特性，并且可以通过减少的凹陷效应来平坦化。

公开(公告)号：US6071792A

公开(公告)日：2000-06-06

申请号：US950325

申请日：1997-10-14

申请人： Chang-gyu Kim ,  Min-su Baek ,  Seok-ji Hong

发明人： Chang-gyu Kim ,  Min-su Baek ,  Seok-ji Hong

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g., SiO.sub.2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self-aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask. Then, the mask and second portions of the electrically insulating layer extending opposite the mask, are etched in sequence to define an electrically insulating region in the trench. This latter etching step is preferably not performed using a chemical mechanical polishing step to limit the likelihood of isolation deterioration caused by the dishing phenomenon.

摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其上具有表面的半导体衬底中形成沟槽，然后在半导体衬底上沉积电绝缘层，以填充沟槽。 该沉积步骤优选通过使用等离子体化学蒸气沉积电绝缘层（例如SiO 2）来进行。 然后在电绝缘层上形成掩模层。 根据本发明的优选方面，使用化学机械抛光对掩模层进行平面化，例如，以限定其中具有开口的掩模，其暴露出与表面相对延伸的电绝缘层的第一部分。 这些第一部分也自对准并延伸到衬底的相对的有效部分。 然后使用掩模作为蚀刻掩模蚀刻电绝缘层的暴露部分。 然后，与掩模相对延伸的掩模和电绝缘层的第二部分依次蚀刻，以在沟槽中限定电绝缘区域。 优选不使用化学机械抛光步骤来进行后一蚀刻步骤，以限制由凹陷现象引起的隔离劣化的可能性。