公开(公告)号：US6001696A

公开(公告)日：1999-12-14

申请号：US52453

申请日：1998-03-31

申请人： Chang-gyu Kim ,  Min-su Baek ,  Ji-hyun Choi

发明人： Chang-gyu Kim ,  Min-su Baek ,  Ji-hyun Choi

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.

摘要翻译： 用于集成电路的隔离方法使用绝缘层的等离子体化学气相沉积，然后剥离以去除绝缘层的至少一部分。 特别地，在集成电路基板上形成剥离层。 在剥离层下方的剥离层和集成电路基板被蚀刻以在集成电路基板中形成沟槽。 沟槽限定在沟槽的一侧上的第一区域和比沟槽另一侧上的第一区域窄的第二区域。 然后进行等离子体化学气相沉积以在第一区域和第二区域上形成填充沟槽的绝缘层，第一区域上的绝缘层比第二区域厚。 然后蚀刻绝缘层以暴露第二区域中的剥离层。 然后将剥离层从第一区域提起。 如此形成的绝缘沟槽可以具有改进的隔离特性，并且可以通过减少的凹陷效应来平坦化。

公开(公告)号：US6071792A

公开(公告)日：2000-06-06

申请号：US950325

申请日：1997-10-14

申请人： Chang-gyu Kim ,  Min-su Baek ,  Seok-ji Hong

发明人： Chang-gyu Kim ,  Min-su Baek ,  Seok-ji Hong

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g., SiO.sub.2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self-aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask. Then, the mask and second portions of the electrically insulating layer extending opposite the mask, are etched in sequence to define an electrically insulating region in the trench. This latter etching step is preferably not performed using a chemical mechanical polishing step to limit the likelihood of isolation deterioration caused by the dishing phenomenon.

摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其上具有表面的半导体衬底中形成沟槽，然后在半导体衬底上沉积电绝缘层，以填充沟槽。 该沉积步骤优选通过使用等离子体化学蒸气沉积电绝缘层（例如SiO 2）来进行。 然后在电绝缘层上形成掩模层。 根据本发明的优选方面，使用化学机械抛光对掩模层进行平面化，例如，以限定其中具有开口的掩模，其暴露出与表面相对延伸的电绝缘层的第一部分。 这些第一部分也自对准并延伸到衬底的相对的有效部分。 然后使用掩模作为蚀刻掩模蚀刻电绝缘层的暴露部分。 然后，与掩模相对延伸的掩模和电绝缘层的第二部分依次蚀刻，以在沟槽中限定电绝缘区域。 优选不使用化学机械抛光步骤来进行后一蚀刻步骤，以限制由凹陷现象引起的隔离劣化的可能性。

公开(公告)号：US06214735B1

公开(公告)日：2001-04-10

申请号：US09080874

申请日：1998-05-18

申请人： Chang-gyu Kim ,  Ji-hyun Choi ,  Seok-ji Hong

发明人： Chang-gyu Kim ,  Ji-hyun Choi ,  Seok-ji Hong

IPC分类号： H01L21311

CPC分类号： H01L21/31055

摘要： A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

摘要翻译： 半导体衬底的平面化方法使用半导体衬底上的绝缘体的蚀刻选择性差。 该方法包括以下步骤：在升高区域的上边缘处湿蚀刻第二绝缘层和第一绝缘层，直到第一绝缘层的部分在上边缘处露出，在第一和第二绝缘层上形成第三绝缘层，以及 湿蚀刻第三绝缘层和第二绝缘层，直到第一绝缘层的上表面露出。 在湿蚀刻期间，第二绝缘层被蚀刻得比第三绝缘层快。 利用该方法，半导体衬底具有均匀的表面。

公开(公告)号：US5795811A

公开(公告)日：1998-08-18

申请号：US578921

申请日：1995-12-27

申请人： Chang-gyu Kim ,  Woo-in Chung

发明人： Chang-gyu Kim ,  Woo-in Chung

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L21/76224

摘要： A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a semiconductor substrate, exposing a portion of the semiconductor substrate in which a device isolation region is to be formed by selectively etching the first and second material layers, forming side wall spacers on exposed lateral sidewalls of the first and second material layers, forming a trench by etching the exposed portion of the semiconductor substrate using the side wall spacers as a mask, depositing an insulating film having an underlayer dependency characteristic over the surface of the resulting structure, etching the surface of the insulating film, and removing the first and second material layers.

摘要翻译： 一种在半导体器件中形成隔离沟槽器件的方法，包括以下步骤： 在半导体衬底的表面上顺序地形成第一材料层和第二材料层，通过选择性地蚀刻第一和第二材料层来暴露要形成器件隔离区的半导体衬底的一部分，形成侧壁间隔物 在第一和第二材料层的暴露的侧壁上，通过使用侧壁间隔物作为掩模蚀刻半导体衬底的暴露部分形成沟槽，在所得结构的表面上沉积具有底层依赖特性的绝缘膜， 蚀刻绝缘膜的表面，以及去除第一和第二材料层。

公开(公告)号：US5866466A

公开(公告)日：1999-02-02

申请号：US730463

申请日：1996-10-15

申请人： Chang-gyu Kim ,  Jae-deok Kim

发明人： Chang-gyu Kim ,  Jae-deok Kim

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76235 ,  H01L21/76202

摘要： An isolation region is formed on a substrate by forming spaced apart mesas on the substrate, each mesa including a barrier region which caps the mesa. An insulation riser is then formed in the substrate, disposed between and separated from the spaced apart mesas. Spaced apart trenches are formed in the substrate on opposite sides of the insulation riser, each trench disposed between the insulation riser and a respective one of the mesas. An insulating material layer is formed on the substrate, the insulating material layer filling the spaced apart trenches and covering the insulation riser and the mesas, and then is chemical mechanical polished to expose the mesas and thereby form an isolation region spanning the spaced apart trenches. Preferably, barrier spacers are formed on sidewall portions of the mesas, and a surface portion of the substrate between the barrier regions is thermally oxidized using the barrier regions and the barrier spacers as an oxidation barrier to form the insulation riser. The isolation region includes an insulation riser at the surface of the substrate, extending from the surface into the substrate, and an insulation region on the substrate, covering the insulation riser and extending into the spaced apart trenches. The insulation region may include insulation spacers adjacent sidewall portions of the spaced apart trenches, and an insulation region on the substrate, covering the insulation riser and extending into the spaced apart trenches to contact the insulation spacers.

摘要翻译： 通过在衬底上形成间隔开的台面，在衬底上形成隔离区域，每个台面包括覆盖台面的阻挡区域。 然后在衬底中形成绝缘提升器，其设置在间隔开的台面之间并与间隔开的台面分离。 在绝缘提升管的相对侧上的衬底中形成间隔开的沟槽，每个沟槽设置在绝缘提升器和相应的台面之间。 在衬底上形成绝缘材料层，绝缘材料层填充间隔开的沟槽并覆盖绝缘提升管和台面，然后进行化学机械抛光以暴露台面，从而形成跨越间隔开的沟槽的隔离区域。 优选地，在台面的侧壁部分上形成阻挡间隔物，并且使用阻挡区域和阻挡间隔物作为氧化屏障来将阻挡区域之间的衬底的表面部分热氧化以形成绝缘提升器。 隔离区域包括在衬底表面延伸到衬底中的绝缘提升器，以及衬底上的绝缘区域，覆盖绝缘提升管并延伸到间隔开的沟槽中。 绝缘区域可以包括与间隔开的沟槽的侧壁部分相邻的绝缘间隔物，以及衬底上的绝缘区域，覆盖绝缘提升管并延伸到间隔开的沟槽中以接触绝缘间隔物。