公开(公告)号：US20120297355A1

公开(公告)日：2012-11-22

申请号：US13112098

申请日：2011-05-20

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。 通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。 将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。 虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。 确定设计是否改进。 当设计没有改进时，创建最终的布局解决方案。

公开(公告)号：US08495534B2

公开(公告)日：2013-07-23

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

公开(公告)号：US08347257B2

公开(公告)日：2013-01-01

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

公开(公告)号：US20110302544A1

公开(公告)日：2011-12-08

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

公开(公告)号：US20110302545A1

公开(公告)日：2011-12-08

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

公开(公告)号：US08108819B2

公开(公告)日：2012-01-31

申请号：US12420156

申请日：2009-04-08

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/08

摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

摘要翻译： 在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。 收到与设计相对应的初始放置。 估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。 在初始位置的一部分上进行变换，包括改善特征的区域。 如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。 该变换可以是调整对象的大小，加权连接，​​聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。

公开(公告)号：US20100262944A1

公开(公告)日：2010-10-14

申请号：US12420156

申请日：2009-04-08

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/08

摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

摘要翻译： 在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。 收到与设计相对应的初始放置。 估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。 在初始位置的一部分上进行变换，包括改善特征的区域。 如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。 该变换可以是调整对象的大小，加权连接，​​聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。

公开(公告)号：US20120284733A1

公开(公告)日：2012-11-08

申请号：US13550957

申请日：2012-07-17

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F9/46

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。

公开(公告)号：US08245173B2

公开(公告)日：2012-08-14

申请号：US12359369

申请日：2009-01-26

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。

公开(公告)号：US08578315B2

公开(公告)日：2013-11-05

申请号：US13550957

申请日：2012-07-17

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.