公开(公告)号：US4399506A

公开(公告)日：1983-08-16

申请号：US194639

申请日：1980-10-06

申请人： Charles W. Evans ,  Frederick O. Flusche ,  Benedicto U. Messina ,  Ethel L. Richardson ,  James R. Robinson ,  Joseph A. Wetzel

发明人： Charles W. Evans ,  Frederick O. Flusche ,  Benedicto U. Messina ,  Ethel L. Richardson ,  James R. Robinson ,  Joseph A. Wetzel

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F9/06

CPC分类号： G06F12/0822

摘要： Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS).Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage.In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

摘要翻译： 当CPU向主存储（MS）发出清除行（CL）命令时，禁止意味着防止存储缓存（SIC）从MS请求或接收任何线路提取。 提供两种CPU模式：（1）初始存储验证模式和（2）指令处理模式。 系统操作员控制第一模式，以便CPU可以在系统初始化期间执行CL命令，而无需从MS获取任何先前的数据。 在第二模式中，作为从MS取出的可以清除主存储器中的块的程序指令的组成部分执行CL命令。 在多处理器（MP）中，任何CPU的CL命令只有在搜索每个其他SIC复制目录并且任何发现的冲突行无效之后才将填充数据的行存储器请求到MS中的寻址行。 对于CS命令在高速缓存中发现的冲突行禁止向MS执行线路切换，这将是其他类型CPU命令的正常操作。 在MP中任何其他高速缓存发现任何线路冲突后，通过取消对MS的线路板写入请求来延迟CL命令的完成。 然后IE重复重新发出CL命令，直到所有发现的冲突行无效。 一旦在任何副本目录中没有发现任何冲突，则当前发出的CL命令是通过不取消对MS的焊盘数据请求来完成的，这样焊盘字节然后被写入MS中的行。

公开(公告)号：US4271468A

公开(公告)日：1981-06-02

申请号：US91902

申请日：1979-11-06

申请人： Neal T. Christensen ,  William C. Van Loo ,  Robert H. Werner ,  Joseph A. Wetzel ,  Carl Zeitler, Jr.

发明人： Neal T. Christensen ,  William C. Van Loo ,  Robert H. Werner ,  Joseph A. Wetzel ,  Carl Zeitler, Jr.

IPC分类号： G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177 ,  G06F15/00

CPC分类号： G06F13/26

摘要： The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty.A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs.In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask non-empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state.Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queue at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP.An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends its acceptance of the corresponding queue, so that any CP can select the next entry on the corresponding queue.When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state.