公开(公告)号：US4456954A

公开(公告)日：1984-06-26

申请号：US273532

申请日：1981-06-15

申请人： Robert J. Bullions, III ,  Thomas O. Curlee, III ,  Peter H. Gum ,  Bruce L. McGilvray ,  Ethel L. Richardson

发明人： Robert J. Bullions, III ,  Thomas O. Curlee, III ,  Peter H. Gum ,  Bruce L. McGilvray ,  Ethel L. Richardson

IPC分类号： G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G06F9/32

CPC分类号： G06F12/1063 ,  G06F9/44 ,  G06F9/45558 ,  G06F2009/45566 ,  G06F2009/45583

摘要： Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

摘要翻译： 在中央处理器（CP）中提供翻译旁边缓冲器（TLB）硬件，中央处理器（CP）接收双层地址转换的结果，以消除在虚拟机（VM）环境中为第二级提供影子表的需要。 硬件被提供用于指示用于转换的CP指令执行（IE）单元发送的请求地址是来宾还是主机/本机请求，以及客户请求是否为真实或虚拟地址。 双级转换的中间翻译可能被禁止或不被禁止加载到TLB中。 访客条目可以从TLB清除，而不会干扰任何主机条目。 CP中加速的首选访客模式迫使单级转换硬件翻译每个加速的首选客人请求。 非加速访客请求可能会被微代码翻译。 提供限制检查寄存器来检查优先访客地址，而不会导致性能下降。

公开(公告)号：US4399506A

公开(公告)日：1983-08-16

申请号：US194639

申请日：1980-10-06

申请人： Charles W. Evans ,  Frederick O. Flusche ,  Benedicto U. Messina ,  Ethel L. Richardson ,  James R. Robinson ,  Joseph A. Wetzel

发明人： Charles W. Evans ,  Frederick O. Flusche ,  Benedicto U. Messina ,  Ethel L. Richardson ,  James R. Robinson ,  Joseph A. Wetzel

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F9/06

CPC分类号： G06F12/0822

摘要： Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS).Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage.In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

摘要翻译： 当CPU向主存储（MS）发出清除行（CL）命令时，禁止意味着防止存储缓存（SIC）从MS请求或接收任何线路提取。 提供两种CPU模式：（1）初始存储验证模式和（2）指令处理模式。 系统操作员控制第一模式，以便CPU可以在系统初始化期间执行CL命令，而无需从MS获取任何先前的数据。 在第二模式中，作为从MS取出的可以清除主存储器中的块的程序指令的组成部分执行CL命令。 在多处理器（MP）中，任何CPU的CL命令只有在搜索每个其他SIC复制目录并且任何发现的冲突行无效之后才将填充数据的行存储器请求到MS中的寻址行。 对于CS命令在高速缓存中发现的冲突行禁止向MS执行线路切换，这将是其他类型CPU命令的正常操作。 在MP中任何其他高速缓存发现任何线路冲突后，通过取消对MS的线路板写入请求来延迟CL命令的完成。 然后IE重复重新发出CL命令，直到所有发现的冲突行无效。 一旦在任何副本目录中没有发现任何冲突，则当前发出的CL命令是通过不取消对MS的焊盘数据请求来完成的，这样焊盘字节然后被写入MS中的行。

公开(公告)号：US4388688A

公开(公告)日：1983-06-14

申请号：US320153

申请日：1981-11-10

申请人： Thomas O. Curlee, III ,  Ethel L. Richardson

发明人： Thomas O. Curlee, III ,  Ethel L. Richardson

IPC分类号： G06F11/00 ,  G06F1/14 ,  G06F9/48 ,  G06F11/30

CPC分类号： G06F9/4825 ,  G06F1/14

摘要： A shared time-of-day (TOD) clock modification bit is used in a multiprocessing system in which the timing facilities in two or more CPUs are implemented as a function of a single TOD clock. This bit helps avoid timer errors that occur as the result of one central processing unit (CPU) changing the TOD clock value while another CPU is executing an instruction which determines a CPU timer value. Whenever the microcode in any one of the CPUs reads the TOD clock, it obtains the Shared TOD Clock Modification Bit in addition to the TOD value. This bit indicates if the TOD clock read operation just completed is the first such operation executed by that CPU since the TOD clock was updated by another CPU sharing the same TOD clock. If it is, certain instructions take action to correct timer errors introduced by the change in the TOD clock value.

摘要翻译： 在多处理系统中使用共享时钟（TOD）时钟修改位，其中两个或更多个CPU中的定时设施被实现为单个TOD时钟的函数。 该位有助于避免由于一个中央处理单元（CPU）更改TOD时钟值而导致的定时器错误，而另一个CPU正在执行确定CPU定时器值的指令。 每当CPU中的任何一个微代码读取TOD时钟时，除了TOD值之外，它都获得共享TOD时钟修改位。 该位指示是否刚刚完成的TOD时钟读取操作是由该CPU执行的第一个这样的操作，因为TOD时钟由共享相同TOD时钟的另一个CPU更新。 如果是，某些指令会采取行动来纠正由TOD时钟值变化引起的定时器错误。