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公开(公告)号：US20220077196A1
公开(公告)日：2022-03-10
申请号：US17461731
申请日：2021-08-30
发明人： Bo WU , Yin DENG , Dongmei WEI , Hao LUO
IPC分类号： H01L27/12 , G02F1/1362
摘要： An array substrate includes a gate layer, a first insulating layer, a channel layer, a source-drain layer, a second insulating layer, and a common electrode layer that are sequentially stacked, wherein the second insulating lay is provided with via holes formed therein; and the source-drain layer includes a plurality of sources, a plurality of drains, a plurality of data lines and a plurality of common electrode signal lines. The common electrode signal line includes a plurality of common electrode signal line segments, each of the common electrode signal line segments passes through at least one sub-pixel row, and each of the common electrode signal line segments is connected to the common electrode layer through the via hole.
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公开(公告)号：US20230152657A1
公开(公告)日：2023-05-18
申请号：US17915110
申请日：2021-11-09
发明人： Hao LUO
IPC分类号： G02F1/16766 , G02F1/167
CPC分类号： G02F1/16766 , G02F1/167
摘要： Provided is an electronic paper. The electronic paper includes: an array substrate and a cover plate that are arranged oppositely, and an electrophoretic layer disposed between the array substrate and the cover plate. The array substrate includes: a substrate, a pixel electrode disposed on the substrate, a first auxiliary electrode disposed on the substrate and electrically connected to the pixel electrode, and a second auxiliary electrode disposed between the pixel electrode and the first auxiliary electrode, wherein the second auxiliary electrode is insulated from the pixel electrode and the first auxiliary electrode. An orthographic projection of the second auxiliary electrode on the substrate is at least partly overlapped with an orthographic projection of the pixel electrode on the substrate, and is at least partly overlapped with an orthographic projection of the first auxiliary electrode on the substrate.
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公开(公告)号：US20210358361A1
公开(公告)日：2021-11-18
申请号：US16470534
申请日：2018-11-19
摘要： A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.
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公开(公告)号：US20210191481A1
公开(公告)日：2021-06-24
申请号：US16895423
申请日：2020-06-08
发明人： Yin DENG , Hao LUO , Ting LI , Bo WU , Dongmei WEI , Chaoguan GONG
摘要： The present disclosure relates to the field of display technology, and provides an array substrate and a display panel. The array substrate is provided with a via hole and further includes an annular wiring area. The annular wiring area is located around the via hole and is provided with an incision extending toward an outer edge of the annular wiring area along an inner edge of the annular wiring area, and at least a portion of the annular wiring area is bent toward a side away from a display side along the inner edge.
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公开(公告)号：US20210183896A1
公开(公告)日：2021-06-17
申请号：US17007780
申请日：2020-08-31
发明人： Dongmei WEI , Hao LUO , Bo WU
IPC分类号： H01L27/12
摘要： An array substrate includes a base, a plurality of thin film transistors, a passivation layer, at least one reflective electrode, and at least one first connecting electrode. The array substrate has a display area. The thin film transistors are disposed in the display area on the base. The passivation layer covers the thin film transistors, and has at least one first via hole in the display area. The reflective electrode is disposed on a surface of the passivation layer facing away from the base, and is disposed in the display area and uncovers the first via hole. The first connecting electrode is disposed on a side of the reflective electrode away from the base. Each first connecting electrode is connected to a corresponding reflective electrode, and is connected to a source or a drain of a corresponding thin film transistor through a corresponding first via hole.
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公开(公告)号：US20230123019A1
公开(公告)日：2023-04-20
申请号：US17915173
申请日：2021-10-28
发明人： Hao LUO , Bo WU , Dongmei WEI , Yin DENG , Zhengdong ZHANG , Yao LI
IPC分类号： H01L27/12 , G02F1/167 , G02F1/1685 , G02F1/1676 , G02F1/1368 , G02F1/1333 , G02F1/1362
摘要： The present disclosure provides a display substrate, a manufacturing method thereof and a display apparatus, and relates to the field of display technology. The manufacturing method of a display substrate includes providing a base substrate, and forming pixels on the base substrate, wherein the forming pixels includes: forming a first auxiliary electrode on the base substrate; forming a first interlayer insulating layer on a side of the first auxiliary electrode away from the base substrate; sequentially forming a second conductive film and a first photoresist layer, exposing the first photoresist layer with a mask plate having regions of different light transmittances by controlling exposure time based on requirements on an operating frequency band of the pixels, to form a source electrode and a drain electrode of the thin film transistor and a second auxiliary electrode, forming a second interlayer insulating layer; and forming a pixel electrode.
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公开(公告)号：US20220121079A1
公开(公告)日：2022-04-21
申请号：US17446121
申请日：2021-08-26
发明人： Hao LUO , Yin DENG , Bo WU , Dongmei WEI
IPC分类号： G02F1/16766 , G02F1/167 , G02F1/16755
摘要： The present disclosure provides an electronic paper display module, including an array substrate and an electronic paper film arranged opposite to each other. The electronic paper film includes a common electrode, the array substrate includes a display region and a peripheral region, and a common electrode lead is located at the peripheral region. An orthogonal projection of the electronic paper film onto the array substrate at least covers the display region, and the common electrode lead is provided with a hollowed-out region.
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公开(公告)号：US20210336218A1
公开(公告)日：2021-10-28
申请号：US16329302
申请日：2018-08-20
发明人： Quanguo ZHOU , Hao LUO
摘要： A display panel, a preparation method thereof, and a display device, and relates to the field of display technology are provided. The display panel includes: a substrate; a plurality of illuminating pixels arranged in an array above the substrate and located in the display region; and a first water oxygen barrier bar disposed above the substrate and located in the peripheral region, wherein the first water oxygen barrier bar includes a plurality of first sub-barrier bars arranged intermittently and a plurality of second sub-barrier bars arranged intermittently; in a direction perpendicular to an arrangement direction of the first sub-barrier bars, a gap between adjacent first sub-barrier bars and a gap between adjacent second sub-barrier bars are not aligned with each other.
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公开(公告)号：US20170269764A1
公开(公告)日：2017-09-21
申请号：US15214363
申请日：2016-07-19
发明人： Hao LUO , Quanguo ZHOU
IPC分类号： G06F3/041
CPC分类号： G06F3/0418 , G06F3/044
摘要： Disclosed is a touch sensing circuit which includes: a compensating module configured to provide a compensating voltage at a first node in response to control signals from a plurality of control signal lines; a read control module configured to transfer a voltage sensed by a touch sensing electrode to the first node in response to a read control signal from a read control signal line, so that the first node has a voltage which is a sum of the compensating voltage and the sensed voltage; and a driving module configured to provide an output signal associated with the sensed voltage to an output signal line in response to the voltage of the first node. Also disclosed are a touch panel and a display device.
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10.发明申请公开(公告)号：US20210192997A1
公开(公告)日：2021-06-24
申请号：US16944431
申请日：2020-07-31
发明人： Hao LUO , Dongmei WEI , Yin DENG
IPC分类号： G09G3/00
摘要： The present disclosure relates to a detection circuit. The detection circuit includes a first input circuit and a second input circuit. The first input circuit has multiple first switch units, each of which being disposed in a one-to-one correspondence with one of multiple first signal lines. The second input circuit has multiple second switch units connected in a cascade arrangement, each of which being disposed in a one-to-one correspondence with one of multiple first signal lines. A second terminal of the second switch unit in a previous stage is connected to a first terminal of the second switch unit in the next adjacent stage. The first terminal of the second switch unit of a first stage is connected to a second terminal of a corresponding first signal line. The second terminal of the second switch unit of a last stage is connected to a first detection terminal.
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