公开(公告)号：US20240312414A1

公开(公告)日：2024-09-19

申请号：US18275013

申请日：2022-07-21

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  Chengdu BOE Optoelectronics Technology Co., Ltd.

发明人： Hongting LU ,  Hang DONG ,  Xing HUANG ,  Xingyu CHEN ,  Lian XIANG ,  Yanping REN ,  Xueying HE ,  Changlong YUAN

IPC分类号： G09G3/3241 ,  G09G3/20 ,  G11C19/28

CPC分类号： G09G3/3241 ,  G11C19/287 ,  G09G3/2074 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2320/043

摘要： A display panel and a display device. The display panel comprises: a substrate, a display area (100) provided with at least one light-emitting signal line (E), at least one first reset signal line (R) and sub-pixels arranged in an array, at least one sub-pixel (P1, P2, P3) comprising: a light-emitting device (L) and a pixel circuit. The first reset signal line (R) is configured to provide a reset control signal for the pixel circuit, the light-emitting signal line is configured to provide a light-emitting control signal for the pixel circuit to provide a driving current. For the first reset signal line and the light-emitting signal line connected to a same pixel circuit, the duration in which the signal of the light-emitting signal line is an invalid level signal is equal to the duration in which the signal of the first reset signal line is a valid level signal.

公开(公告)号：US20240274074A1

公开(公告)日：2024-08-15

申请号：US18022753

申请日：2022-02-28

申请人： Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

发明人： Yanping REN ,  Hongting LU ,  Lian XIANG ,  Xingyu CHEN ,  Chao YANG ,  Yan YANG

IPC分类号： G09G3/3233

CPC分类号： G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2330/02

摘要： Provided is a drive control circuit, which includes an input circuit (10), a first output circuit (11) and a second output circuit (12). An input circuit (10) is configured to control the potentials of a first node (N1) and a second node (N2) under the control of a signal input terminal (INT) and a clock signal terminal. The first output circuit (11) is configured to output a first power supply signal supplied by a first power supply line (VGH1) to a first output terminal (OUT1) under the control of a first node (N1), or to output a second power supply signal supplied by a second power supply line (VGL1) to the first output terminal (OUT1) under the control of a second node (N2).