Folding systolic architecture for comma-free reed-solomon decoding circuit
    1.
    发明授权
    Folding systolic architecture for comma-free reed-solomon decoding circuit 有权
    折叠收缩结构,用于无逗号的芦苇解码电路

    公开(公告)号:US06928600B2

    公开(公告)日:2005-08-09

    申请号:US10122185

    申请日:2002-04-16

    IPC分类号: H03M13/15 H03M13/33

    CPC分类号: H03M13/15

    摘要: A kind of folding systolic array architecture for a CFRS decoding circuit that applies to a cell search in a wideband code division multiple access system. The invention involves using a systolic array for its decoding circuit and using a kind of folding technology to reduce the area of the systolic array. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a set of correlating comparisons, and outputs the results of the correlating comparisons to the boundary processing elements, so as to acquire the decoding results required by the CFRS decoding. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

    摘要翻译: 一种用于CFRS解码电路的折叠式收缩阵列架构,适用于宽带码分多址系统中的小区搜索。 本发明涉及使用收缩阵列作为其解码电路,并使用一种折叠技术来减小收缩阵列的面积。 用于解码电路的收缩阵列包括输入图案生成器,以心轴阵列和边界处理元件阵列的形式设计的处理元件阵列。 给定收缩阵列所需的偏斜形式输出结果并由输入模式发生器产生,处理单元阵列进行一组相关比较,并将相关比较的结果输出到边界处理单元,以获得 CFRS解码所需的解码结果。 结果表明宽带码分多址系统中小区搜索的帧边界和扰码组。

    Weighted decoding method and circuits for Comma-Free Reed-Solomon codes
    2.
    发明授权
    Weighted decoding method and circuits for Comma-Free Reed-Solomon codes 有权
    加密解码方法和电路,用于Comma-Free Reed-Solomon码

    公开(公告)号:US06944813B2

    公开(公告)日:2005-09-13

    申请号:US10120546

    申请日:2002-04-12

    IPC分类号: H03M13/15

    CPC分类号: H03M13/15

    摘要: A weighted decoding method and circuits for Comma-Free Reed-Solomon codes that apply to a cell search in a wideband code division multiple access system. The invention also provides a weighted decoding method wherein the decoding result of the secondary synchronization code is used as a weight for received Comma-Free Reed-Solomon symbol data, and the weighted symbol data is input to the processing element array of the decoding circuit, so as to perform a weighted correlating comparison and thus enhance the accuracy of the decoding result. The weighted decoding method put forward by the invention may apply to a decoding architecture that is based on a systolic array and the decoding architecture that is based on a folding systolic array.

    摘要翻译: 一种适用于宽带码分多址系统中的小区搜索的无逗号里德 - 所罗门码的加权解码方法和电路。 本发明还提供一种加权解码方法,其中将辅同步码的解码结果用作接收到的无逗点里德 - 索洛蒙符号数据的权重,并将加权符号数据输入到解码电路的处理元件阵列, 从而进行加权相关比较,从而提高解码结果的准确性。 本发明提出的加权解码方法可以应用于基于收缩阵列和基于折叠式心脏收缩阵列的解码架构的解码架构。

    Systolic architecture for Comma-Free Reed-Solomon decoding circuit
    3.
    发明授权
    Systolic architecture for Comma-Free Reed-Solomon decoding circuit 有权
    无声Reed-Solomon解码电路的收缩架构

    公开(公告)号:US07051263B2

    公开(公告)日:2006-05-23

    申请号:US10120536

    申请日:2002-04-12

    IPC分类号: H03M13/15

    CPC分类号: H03M13/15

    摘要: A Comma-Free Reed-Solomon decoding circuit based on systolic array architecture that applies to a cell search in a wideband code division multiple access system, and more particularly a decoding circuit that employs a systolic array in its circuit structure. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a correlating comparison, and outputs the results of the correlating comparison to the boundary processing element, so as to acquire the decoding results required by the Comma-Free Reed-Solomon code. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

    摘要翻译: 一种适用于宽带码分多址系统中的小区搜索的基于收缩阵列架构的无逗号里德 - 索罗门解码电路,更具体地说,在其电路结构中采用收缩阵列的解码电路。 用于解码电路的收缩阵列包括输入图案生成器,以心轴阵列和边界处理元件阵列的形式设计的处理元件阵列。 给定收缩阵列所需的偏斜形式输出结果并由输入模式发生器产生,处理单元阵列进行相关比较,并将相关比较的结果输出到边界处理单元,以获得解码结果 所需的免费Reed-Solomon码。 结果表明宽带码分多址系统中小区搜索的帧边界和扰码组。