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    Method for automatically generating checkers for finding functional defects in a description of a circuit
    4.
    发明授权
    Method for automatically generating checkers for finding functional defects in a description of a circuit 有权
    一种用于自动生成检查器以查找电路描述中的功能缺陷的方法

    公开(公告)号：US06609229B1

    公开(公告)日：2003-08-19

    申请号：US09635598

    申请日：2000-08-09

    申请人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    发明人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022

    摘要： A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

    摘要翻译： 编程的计算机产生标记正在进行功能验证的电路的描述中的功能缺陷的电路（称为“检查器”）的描述。 编程的计算机自动将电路的描述转换为图形，自动检查图表中预定布置的节点和连接的实例，并自动生成指示，该指令根据已知的缺陷行为标记由实例表示的设备的行为。 在仿真或模拟电路期间或在半导体管芯中的电路操作期间可以使用检查器。电路的描述可以在Verilog或VHDL中，自动生成的检查器也可以在Verilog或VHDL中描述。 因此，检查器可以与电路共同模拟，监测电路的仿真操作和标记检测行为。 编程的计算机可以自动确定电路中寄存器的负载条件，并自动生成检查器以标志寄存器中的数据丢失。 一些检查者可能会使用其他检查器产生的信号。

    Method for automatically generating checkers for finding functional defects in a description of a circuit
    6.
    发明授权
    Method for automatically generating checkers for finding functional defects in a description of a circuit 失效
    一种用于自动生成检查器以查找电路描述中的功能缺陷的方法

    公开(公告)号：US06175946B1

    公开(公告)日：2001-01-16

    申请号：US08955329

    申请日：1997-10-20

    申请人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    发明人： Tai An Ly ,  Jean-Charles Giomi ,  Kalyana C. Mulam ,  Paul Andrew Wilcox ,  David Lansing Dill ,  Paul Estrada, II ,  Chian-Min Richard Ho ,  Jing Chyuarn Lin ,  Robert Kristianto Mardjuki ,  Lawrence Curtis Widdoes, Jr. ,  Ping Fai Yeung

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022

    摘要： A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

    摘要翻译： 编程的计算机产生标记正在进行功能验证的电路的描述中的功能缺陷的电路（称为“检查器”）的描述。 编程的计算机自动将电路的描述转换为图形，自动检查图表中预定布置的节点和连接的实例，并自动生成指示，该指令根据已知的缺陷行为标记由实例表示的设备的行为。 可以在仿真或模拟电路期间或在半导体管芯中的电路操作期间使用检查器。 电路的描述可以在Verilog或VHDL中，自动生成的检查器也可以在Verilog或VHDL中描述。 因此，检查器可以与电路共同模拟，监视电路的模拟操作并标记有缺陷的行为。 编程的计算机可以自动确定电路中寄存器的负载条件，并自动生成检查器以标志寄存器中的数据丢失。 一些检查者可能会使用其他检查器产生的信号。